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HY57V651620BTC-6I PDF预览

HY57V651620BTC-6I

更新时间: 2024-11-06 21:05:43
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器ISM频段光电二极管内存集成电路
页数 文件大小 规格书
11页 141K
描述
Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57V651620BTC-6I 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:54
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.28
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G54
JESD-609代码:e6长度:22.22 mm
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:4MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN BISMUTH
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

HY57V651620BTC-6I 数据手册

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HY57V651620B  
4 Banks x 1M x 16Bit Synchronous DRAM  
DESCRIPTION  
The Hynix HY57V651620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications  
which require low power consumption and extended temperature range. HY57V651620B is organized as 4banks of  
1,048,576x16.  
HY57V651620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-  
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3V ± 10% power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4096 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm  
of pin pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
Data mask function by UDQM or LDQM  
Internal four banks operation  
Programmable CAS Latency ; 2, 3 Clocks  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V651620BTC-6I  
HY57V651620BTC-7I  
HY57V651620BTC-75I  
HY57V651620BTC-10PI  
HY57V651620BTC-10SI  
HY57V651620BLTC-6I  
HY57V651620BLTC-7I  
HY57V651620BLTC-75I  
HY57V651620BLTC-10PI  
HY57V651620BLTC-10SI  
166MHz  
143MHz  
133MHz  
100MHz  
100MHz  
166MHz  
143MHz  
133MHz  
100MHz  
100Mhz  
Normal  
power  
4Banks x 1Mbits  
x16  
LVTTL  
400mil 54pin TSOP II  
Lower  
Power  
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.7/Nov. 01  

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