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HY57V653220BTC-10P PDF预览

HY57V653220BTC-10P

更新时间: 2024-11-19 22:51:27
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器
页数 文件大小 规格书
12页 155K
描述
4 Banks x 512K x 32Bit Synchronous DRAM

HY57V653220BTC-10P 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSSOP86,.46,20针数:86
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.74
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G86JESD-609代码:e6
长度:22.22 mm内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:86字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSSOP86,.46,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.19 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN BISMUTH端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

HY57V653220BTC-10P 数据手册

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HY57V653220B  
4 Banks x 512K x 32Bit Synchronous DRAM  
DESCRIPTION  
The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications  
which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.  
HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-  
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
JEDEC standard 3.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4096 refresh cycles / 64ms  
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of  
pin pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
Data mask function by DQM0,1,2 and 3  
Internal four banks operation  
Programmable CAS Latency ; 2, 3 Clocks  
Burst Read Single Write operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V653220BTC-5  
HY57V653220BTC-55  
HY57V653220BTC-6  
HY57V653220BTC-7  
HY57V653220BTC-8  
HY57V653220BTC-10P  
HY57V653220BTC-10  
200MHz  
183MHz  
166MHz  
143MHz  
125MHz  
100MHz  
100MHz  
4Banks x 512Kbits  
x32  
Normal  
LVTTL  
400mil 86pin TSOP II  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev.1.6/Dec. 01  
1

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