Datasheet > HY57V654020BTC-6

HY57V654020BTC-6

更新时间： 2024-11-05 23:57:11

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
12页	147K
描述
x4 SDRAM

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HY57V654020BTC-6 数据手册

HY57V654020B

4 Banks x 4M x 4Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V654020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V654020B is organized as 4banks of 4,194,304x4.

HY57V654020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V654020BTC-6

HY57V654020BTC-75

HY57V654020BTC-8

HY57V654020BTC-10P

HY57V654020BTC-10S

HY57V654020BTC-10

HY57V654020BLTC-6

HY57V654020BLTC-75

HY57V654020BLTC-8

HY57V654020BLTC-10P

HY57V654020BLTC-10S

HY57V654020BLTC-10

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits x4

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 1.7/Nov. 01

12 3 4 5 6 7...12

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HY57V654020BTC-8	ETC	获取价格	x4 SDRAM
HY57V654020TC-10	ETC	获取价格	x4 SDRAM
HY57V654020TC-12	ETC	获取价格	x4 SDRAM
HY57V654020TC-15	ETC	获取价格	x4 SDRAM
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HY57V654021TC-10	ETC	获取价格	x4 SDRAM
HY57V654021TC-7	ETC	获取价格	x4 SDRAM
HY57V654021TC-8	ETC	获取价格	x4 SDRAM