Datasheet > HY57V653220BTC

HY57V653220BTC

更新时间： 2024-11-05 22:51:27

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
12页	155K
描述
4 Banks x 512K x 32Bit Synchronous DRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HY57V653220BTC 数据手册

HY57V653220B

4 Banks x 512K x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications

which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.

HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 86pin TSOP-II with 0.5mm of

pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V653220BTC-5

HY57V653220BTC-55

HY57V653220BTC-6

HY57V653220BTC-7

HY57V653220BTC-8

HY57V653220BTC-10P

HY57V653220BTC-10

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

4Banks x 512Kbits

x32

Normal

LVTTL

400mil 86pin TSOP II

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev.1.6/Dec. 01

12 3 4 5 6 7...12

中文翻译

下载PDF

与HY57V653220BTC相关器件

型号	品牌	获取价格	描述	数据表
HY57V653220BTC-10	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V653220BTC-10I	ETC	获取价格	x32 SDRAM
HY57V653220BTC-10P	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V653220BTC-5	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V653220BTC-55	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V653220BTC-6	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V653220BTC-6I	ETC	获取价格	x32 SDRAM
HY57V653220BTC-7	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V653220BTC7DR	HYNIX	获取价格	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86
HY57V653220BTC-7I	ETC	获取价格	x32 SDRAM

与HY57V653220BTC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V653220BTC

HY57V653220BTC 数据手册

与HY57V653220BTC相关器件

与HY57V653220BTC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V653220BTC

HY57V653220BTC 数据手册

与HY57V653220BTC相关器件

与HY57V653220BTC相关文章

您还可以找

您在本页遇到什么问题？