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HY57V653220BLTC-10I PDF预览

HY57V653220BLTC-10I

更新时间: 2024-11-05 23:57:11
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
11页 53K
描述
x32 SDRAM

HY57V653220BLTC-10I 数据手册

 浏览型号HY57V653220BLTC-10I的Datasheet PDF文件第2页浏览型号HY57V653220BLTC-10I的Datasheet PDF文件第3页浏览型号HY57V653220BLTC-10I的Datasheet PDF文件第4页浏览型号HY57V653220BLTC-10I的Datasheet PDF文件第5页浏览型号HY57V653220BLTC-10I的Datasheet PDF文件第6页浏览型号HY57V653220BLTC-10I的Datasheet PDF文件第7页 
HY57V653220B  
4 Banks x 512K x 32Bit Synchronous DRAM  
DE S CRIPT ION  
T h e H y n i x H Y 5 7 V 6 5 3 2 2 0 B i s a 6 7 , 1 0 8 , 8 6 4 - b i t C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e M o b i l e a p p l i c a t i o n s  
which require low power consumption and extended temperature range. HY57V653220B is organized as 4banks of  
524, 288x32.  
H Y 5 7 V 6 5 3 2 2 0 B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-  
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by  
a
single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by  
design is not restricted by a `2N` rule.)  
a new burst read or write command on any cycle. (This pipelined  
F EAT URES  
JEDEC standard 3. 3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4 0 9 6 r e f r e s h c y c l e s / 6 4 m s  
J E D E C s t a n d a r d 4 0 0 m i l 8 6 p i n T S O P - I I w i t h 0 . 5 m m o f  
pin pitch  
P r o g r a m m a b l e B u r s t L e n g t h a n d B u r s t T y p e  
- 1, 2, 4, 8 or full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
D a t a m a s k f u n c t i o n b y D Q M 0 , 1 , 2 a n d 3  
Internal four banks operation  
P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks  
Burst Read Single Write operation  
OR D E R IN G INF ORMAT ION  
Par t No.  
Cl ock Fr equency  
Powe r  
Or gani zat i on  
Int er f ace  
Package  
H Y 5 7 V 6 5 3 2 2 0 B T C - 6 I  
H Y 5 7 V 6 5 3 2 2 0 B T C -7 I  
H Y 5 7 V 6 5 3 2 2 0 B T C - 1 0 I  
H Y 5 7 V 6 5 3 2 2 0 B L T C - 6 I  
H Y 5 7 V 6 5 3 2 2 0 B L T C - 7 I  
H Y 5 7 V 6 5 3 2 2 0 B L T C - 1 0 I  
1 6 6 M H z  
14 3 M H z  
1 0 0 M H z  
1 6 6 M H z  
1 4 3 M H z  
1 0 0 M H z  
4 B a n k s x 5 1 2 K b i t s  
x 3 2  
N o r m a l  
L V T T L  
400mil 86pin TSOP II  
This document is  
a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0. 6/ Aug. 01  

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