Datasheet > HSP45240

HSP45240

更新时间： 2024-11-13 22:48:31

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
6页	145K
描述
Address Sequencer

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数据手册

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HSP45240 数据手册

HSP45240/883

Address Sequencer

February 1998

Features

Description

• This Circuit is Processed in Accordance to MIL-STD- The Intersil HSP45240/883 is a high speed Address

883 and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

Sequencer which provides specialized addressing for func-

tions like FFTs, 1-D and 2-D ﬁltering, matrix operations, and

image manipulation. The sequencer supports block oriented

addressing of large data sets up to 24 bits at clock speeds

up to 40MHz.

• Block Oriented 24-Bit Sequencer

• Conﬁgurable as Two Independent 12-Bit Sequencers

• 24 x 24 Crosspoint Switch

Specialized addressing requirements are met by using the

onboard 24 x 24 crosspoint switch. This feature allows the

mapping of the 24 address bits at the output of the address

generator to the 24 address outputs of the chip. As a result,

bit reverse addressing, such as that used in FFTs, is made

possible.

• Programmable Delay on 12 Outputs 9-

• Multi-Chip Synchronization Signals

• Standard µP Interface

• 100pF Drive on Outputs

A single chip solution to read/write addressing is also made

possible by conﬁguring the HSP45240 as two 12-bit

sequencers. To compensate for system pipeline delay, a pro-

grammable delay is provided on 12 of the address outputs.

• DC to 40MHz Clock Rate

Applications

• 1-D, 2-D Filtering

The HSP45240 is manufactured using an advanced CMOS

process, and is a low power fully static design. The conﬁgu-

ration of the device is controlled through a standard micro-

processor interface and all inputs/outputs, with the exception

of clock, are TTL compatible.

• Pan/Zoom Addressing

• FFT Processing

• Matrix Math Operations

Ordering Information

TEMP.

RANGE ( C)

PKG.

NO.

PART NUMBER

HSP45240GM-25/883

HSP45240GM-33/883

HSP45240GM-40/883

PACKAGE

-55 to 125 68 Ld PGA

Block Diagram

STARTOUT

ADDVAL

DONE

BLOCKDONE

OUT12-23

REG

STARTIN

CROSS-POINT

SWITCH

START

CIRCUITRY

SEQUENCE

GENERATOR

OEH

DELAY

1-8

OUT0-11

DLYBLK

OEL

BUSY

PROCESSOR INTERFACE

D0-6, CS, A0, WR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2816.3

9-16

12 3 4 5 6

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