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HMP512U7FFP8C-Y5 PDF预览

HMP512U7FFP8C-Y5

更新时间: 2024-11-07 05:36:19
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
25页 437K
描述
240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.

HMP512U7FFP8C-Y5 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM240,40
针数:240Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.84Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.45 ns
其他特性:AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX最大时钟频率 (fCLK):333 MHz
I/O 类型:COMMONJESD-30 代码:R-XZMA-N200
长度:133.35 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:8
功能数量:1端口数量:1
端子数量:240字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:128MX8输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM240,40封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:30 mm
自我刷新:YES子类别:Other Memory ICs
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:1 mm
端子位置:ZIG-ZAG处于峰值回流温度下的最长时间:20
宽度:4 mmBase Number Matches:1

HMP512U7FFP8C-Y5 数据手册

 浏览型号HMP512U7FFP8C-Y5的Datasheet PDF文件第2页浏览型号HMP512U7FFP8C-Y5的Datasheet PDF文件第3页浏览型号HMP512U7FFP8C-Y5的Datasheet PDF文件第4页浏览型号HMP512U7FFP8C-Y5的Datasheet PDF文件第5页浏览型号HMP512U7FFP8C-Y5的Datasheet PDF文件第6页浏览型号HMP512U7FFP8C-Y5的Datasheet PDF文件第7页 
240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.  
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2 SDRAMs  
in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb C ver. based  
DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor  
of industry standard. It is suitable for easy interchange and addition.  
FEATURES  
JEDEC standard Double Data Rate2 Synchro-  
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-  
0.1V Power Supply  
Programmable Burst Length 4 / 8 with both  
sequential and interleave mode  
Auto refresh and self refresh supported  
Partial Array Self Refresh supported  
8192 refresh cycles / 64ms  
All inputs and outputs are compatible with  
SSTL_1.8 interface  
4 Bank architecture  
Serial presence detect with EEPROM  
DDR2 SDRAM Package: 60ball FBGA(64Mx8)  
133.35 x 30.00 mm form factor  
Posted CAS  
Programmable CAS Latency 3 , 4 , 5, 6  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
Lead-free Products are RoHS compliant  
Fully differential clock operations (CK & CK)  
ORDERING INFORMATION  
# of  
DRAMs ranks  
# of  
Part Name  
Density Organization  
Materials  
ECC  
HMP512U6FFP8C-Y5/S5/S6  
HMP564U7FFP8C-Y5/S5/S6  
HMP512U7FFP8C-Y5/S5/S6  
1GB  
512MB  
1GB  
128Mx64  
64Mx72  
16  
9
2
1
2
Lead free  
Lead free  
Lead free  
None  
ECC  
128Mx72  
18  
ECC  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.1 / Jun 2008  
1

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