Datasheet > HMP564F7FFP8C-Y5C1

HMP564F7FFP8C-Y5C1

更新时间： 2024-11-07 18:48:23

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器光电二极管
页数	文件大小	规格书
26页	625K
描述
DRAM, 64MX72, CMOS, PDMA240

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技术参数
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HMP564F7FFP8C-Y5C1 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	DIMM, DIMM240,40	Reach Compliance Code：	compliant
风险等级：	5.84	最大时钟频率 (fCLK)：	333 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PDMA-N240
内存密度：	4831838208 bit	内存宽度：	72
端子数量：	240	字数：	67108864 words
字数代码：	64000000	最高工作温度：	95 °C
最低工作温度：		组织：	64MX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIMM	封装等效代码：	DIMM240,40
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
电源：	1.5,1.8 V	认证状态：	Not Qualified
刷新周期：	8192	子类别：	Other Memory ICs
表面贴装：	NO	技术：	CMOS
温度等级：	OTHER	端子形式：	NO LEAD
端子节距：	1 mm	端子位置：	DUAL
Base Number Matches：	1

HMP564F7FFP8C-Y5C1 数据手册

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240pin Fully Buffered DDR2 SDRAM DIMMs based on 512 Mb F-ver.

This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow

host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that

isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of

each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the

host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host

controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point

Link Interface at 1.5V power.

The AMB also allows buffering of memory traffic to support large memory capacities. All memory control

for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,

scrubbing, sparing, configuration access and power management. The AMB interface is responsible for

handling channel and memory requests to and from the local FBDIMM and for forwarding request to other

FBDIMMs on the memory channel.

FEATURES

•

240 pin Fully Buffered ECC dual In-Line DDR2 SDRAM Module

JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply

All inputs and outputs are compatible with SSTL_1.8 interface

Built with 512Mb DDR2 SDRAMs in 60ball FBGA

Host interface and AMB component industry standard compliant

MBIST & IBIST test functions

4 Bank architecture

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

Fully differential clock operations (CK & CK)

Programmable Burst Length 4 / 8 with both sequential and interleave mode

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial presence detect with EEPROM

133.35 x 30.35 mm form factor

RoHS compliant

Full Module Heat Spreader

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev 1.0 / July 2008

12 3 4 5 6 7...26

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与HMP564F7FFP8C-Y5C1相关器件

型号	品牌	获取价格	描述	数据表
HMP564F7FFP8C-Y5D1	HYNIX	获取价格	DRAM, 64MX72, CMOS, PDMA240
HMP564F7FFP8C-Y5D3	HYNIX	获取价格	DDR DRAM, 64MX72, CMOS, ROHS COMPLIANT, DIMM-240
HMP564F7FFP8C-Y5N3	HYNIX	获取价格	240pin Fully Buffered DDR2 SDRAM DIMMs based on 512 Mb F-ver.
HMP564P7FFP8C-Y5	HYNIX	获取价格	240pin Registered DDR2 SDRAM DIMMs based on 512 Mb F ver.
HMP564U7FFP8C-S5	HYNIX	获取价格	240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.
HMP564U7FFP8C-S6	HYNIX	获取价格	240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.
HMP564U7FFP8C-Y5	HYNIX	获取价格	240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.
HMP8112	HARRIS	获取价格	NTSC/PAL Video Decoder
HMP8112ACN	HARRIS	获取价格	NTSC/PAL Video Decoder
HMP8112CN	HARRIS	获取价格	NTSC/PAL Video Decoder

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