Datasheet > HMP564U7FFP8C-S5

HMP564U7FFP8C-S5

更新时间： 2024-09-17 05:36:19

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器双倍数据速率
页数	文件大小	规格书
25页	437K
描述
240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.

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中文翻译

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数据手册

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HMP564U7FFP8C-S5 数据手册

240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.

This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2 SDRAMs

in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb C ver. based

DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor

of industry standard. It is suitable for easy interchange and addition.

FEATURES

•

JEDEC standard Double Data Rate2 Synchro-

nous DRAMs (DDR2 SDRAMs) with 1.8V +/-

0.1V Power Supply

•

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

•

Auto refresh and self refresh supported

Partial Array Self Refresh supported

8192 refresh cycles / 64ms

All inputs and outputs are compatible with

SSTL_1.8 interface

•

4 Bank architecture

Serial presence detect with EEPROM

DDR2 SDRAM Package: 60ball FBGA(64Mx8)

133.35 x 30.00 mm form factor

Posted CAS

Programmable CAS Latency 3 , 4 , 5, 6

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

•

Lead-free Products are RoHS compliant

Fully differential clock operations (CK & CK)

ORDERING INFORMATION

# of

DRAMs ranks

# of

Part Name

Density Organization

Materials

ECC

HMP512U6FFP8C-Y5/S5/S6

HMP564U7FFP8C-Y5/S5/S6

HMP512U7FFP8C-Y5/S5/S6

1GB

512MB

1GB

128Mx64

64Mx72

Lead free

None

ECC

128Mx72

ECC

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1 / Jun 2008

12 3 4 5 6 7...25

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