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HM5225645F-B60 PDF预览

HM5225645F-B60

更新时间: 2024-10-26 22:15:23
品牌 Logo 应用领域
日立 - HITACHI 动态存储器PC
页数 文件大小 规格书
16页 80K
描述
256M LVTTL interface SDRAM 100 MHz 1-Mword x 64-bit x 4-bank/2-Mword x 32-bit x 4-bank PC/100 SDRAM

HM5225645F-B60 数据手册

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HM5225645F-B60  
HM5225325F-B60  
256M LVTTL interface SDRAM  
100 MHz  
1-Mword × 64-bit × 4-bank/2-Mword × 32-bit × 4-bank  
PC/100 SDRAM  
ADE-203-1014C (Z)  
Rev. 1.0  
Oct. 1, 1999  
Description  
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word × 64-bit × 4-bank. The Hitachi  
HM5225325F is a 256-Mbit SDRAM organized as 2097152-word × 32-bit × 4-bank. All inputs and outputs  
are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.  
Features  
Single chip wide bit solution (× 64/× 32)  
3.3 V power supply  
Clock frequency: 100 MHz (max)  
LVTTL interface  
Extremely small foot print: 1.27 mm pitch  
Package: BGA (BP-108)  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 4/8/full page  
2 variations of burst sequence  
Sequential (BL = 4/8/full page)  
Interleave (BL = 4/8)  
Programmable CAS latency: 2/3  
Byte control by DQMB  

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