Datasheet > HM5241605CJ-17

HM5241605CJ-17

更新时间： 2024-10-26 23:56:15

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HM5241605CJ-17 数据手册

HM5241605C Series

4M LVTTL interface SDRAM (128-kword × 16-bit)

83 MHz/80 MHz/66 MHz/57 MHz

ADE-203-381C (Z)

Rev. 3.0

Nov. 11, 1997

Description

All inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2

banks for improved performance.

Features

•

3.3V Power supply

Clock frequency: 80 MHz (V_CCmin = 3.0 V)/66 MHz/57 MHz (max)

: 83 MHz (V_CCmin = 3.15 V)

LVTTL interface

•

Single pulsed RAS

2 Banks can operates simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 1/2/4/8/full page (256)

Programmable burst sequence:

Sequential

Interleave

•

Full page burst length capability

Sequential burst

Burst stop capability

•

Programmable CAS latency: 1/2/3

Byte control by DQMU and DQML

1024 refresh cycles: 16 ms

2 variations of refresh

Auto refresh

Self refresh

12 3 4 5 6 7...57

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型号	品牌	获取价格	描述	数据表
HM5241605CTT-12	ETC	获取价格	x16 SDRAM
HM5241605CTT-15	ETC	获取价格	x16 SDRAM
HM5241605CTT-17	ETC	获取价格	x16 SDRAM
HM5241605TT-15	ETC	获取价格	x16 SDRAM
HM5241605TT-17	ETC	获取价格	x16 SDRAM
HM5241605TT-20	ETC	获取价格	x16 SDRAM
HM5251165B/1805B/1405B-75/A6/B6	ETC	获取价格	512M LVTTL Interface SDRAM 133 MHz/100 MHz 8-Mwo
HM5251805BLTD-B6	HITACHI	获取价格	Synchronous DRAM, 64MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
HM5257165B	ELPIDA	获取价格	512M LVTTL interface SDRAM 133 MHz/100 MHz 8-
HM5257165B-75	ELPIDA	获取价格	512M LVTTL interface SDRAM 133 MHz/100 MHz 8-