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HM5251805BLTD-B6 PDF预览

HM5251805BLTD-B6

更新时间: 2024-10-27 14:51:03
品牌 Logo 应用领域
日立 - HITACHI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
64页 1030K
描述
Synchronous DRAM, 64MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

HM5251805BLTD-B6 数据手册

 浏览型号HM5251805BLTD-B6的Datasheet PDF文件第2页浏览型号HM5251805BLTD-B6的Datasheet PDF文件第3页浏览型号HM5251805BLTD-B6的Datasheet PDF文件第4页浏览型号HM5251805BLTD-B6的Datasheet PDF文件第5页浏览型号HM5251805BLTD-B6的Datasheet PDF文件第6页浏览型号HM5251805BLTD-B6的Datasheet PDF文件第7页 
HM5251165B-75/A6/B6  
HM5251805B-75/A6/B6  
HM5251405B-75/A6/B6  
512M LVTTL interface SDRAM  
133 MHz/100 MHz  
8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank  
/32-Mword × 4-bit × 4-bank  
PC/133, PC/100 SDRAM  
ADE-203-1095 (Z)  
Preliminary  
Rev. 0.0  
Sep. 1, 1999  
Description  
The Hitachi HM5251165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The  
Hitachi HM5251805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The Hitachi  
HM5251405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs  
are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 133 MHz/100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8)  
Interleave (BL = 1/2/4/8)  
Preliminary: The specifications of this device are subject to change without notice. Please contact your  
nearest Hitachi’s Sales Dept. regarding specifications.  

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