Datasheet > HM5225805BTT-B6

HM5225805BTT-B6

更新时间： 2024-10-27 20:19:19

品牌	Logo	应用领域
日立 - HITACHI		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
64页	786K
描述
Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

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HM5225805BTT-B6 数据手册

HM5225165B-75/A6/B6

HM5225805B-75/A6/B6

HM5225405B-75/A6/B6

256M LVTTL interface SDRAM

133 MHz/100 MHz

4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank

/16-Mword × 4-bit × 4-bank

PC/133, PC/100 SDRAM

ADE-203-1073B (Z)

Rev. 1.0

Feb. 10, 2000

Description

The Hitachi HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The

Hitachi HM5225805B is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The Hitachi

HM5225405B is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs

are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features

•

3.3 V power supply

Clock frequency: 133 MHz/100 MHz (max)

LVTTL interface

Single pulsed RAS

4 banks can operate simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 1/2/4/8

2 variations of burst sequence

Sequential (BL = 1/2/4/8)

Interleave (BL = 1/2/4/8)

•

Programmable CAS latency: 2/3

12 3 4 5 6 7...64

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HM5241605CJ-12	ETC	获取价格	x16 SDRAM
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