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HM5225405ATT-8 PDF预览

HM5225405ATT-8

更新时间: 2024-10-27 14:51:03
品牌 Logo 应用领域
日立 - HITACHI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
61页 591K
描述
Synchronous DRAM, 64MX4, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

HM5225405ATT-8 数据手册

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HM5225165A-8/10  
HM5225805A-8/10  
HM5225405A-8/10  
256M LVTTL interface SDRAM  
125 MHz/100 MHz  
4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank  
/16-Mword × 4-bit × 4-bank  
ADE-203-834B (Z)  
Preliminary, Rev. 0.2  
Sept. 20, 1998  
Description  
The Hitachi HM5225165A is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The  
Hitachi HM5225805A is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The Hitachi  
HM5225405A is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and  
outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 125 MHz/100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  

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