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HD74LS190FP-EL PDF预览

HD74LS190FP-EL

更新时间: 2024-11-09 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器逻辑集成电路时钟
页数 文件大小 规格书
11页 198K
描述
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO16, FP-16DA

HD74LS190FP-EL 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknown风险等级:5.67
Is Samacsys:N计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:R-PDSO-G16
长度:10.06 mm负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER工作模式:SYNCHRONOUS
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):36 ns
认证状态:Not Qualified座面最大高度:2.2 mm
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.5 mm
最小 fmax:20 MHzBase Number Matches:1

HD74LS190FP-EL 数据手册

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HD74LS190  
Synchronous Up / Down Decade Counter (signal clock line)  
REJ03D0452–0200  
Rev.2.00  
Jul.15.2005  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident  
with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes  
normally associated with asynchronous (ripple clock) counters.  
The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the  
enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made  
only when the clock input is high. The direction of the count is determined by the level of the down / up input. When  
low, the counter counts up and when high, it counts down. Level changes at the down / up input should be made only  
when the clock input is high. This counter is fully programmable; that is, the outputs may be preset to either level by  
placing a low on the load input and entering the desired data at the data inputs. Toutput will change to agree with the  
data inputs independently of the level of the clock input. This feature allows ters to be used as modulo-N  
dividers by simply modifying the count length with the preset inputs. The cup, and load inputs are  
buffered to lower the drive requirement which significantly reduces the ners, etc., required for long  
parallel words.  
Two outputs have been made available to perform the cascadinmaximum / minimum count.  
The latter output produces a high-level output pulse with a dto one complete cycles to the  
clock when the counter overflows or underflows. The riplow-level output pulse equal in  
width to the low-level portion of the clock input when nditions exists.  
The counters can be easily cascaded by feeding tenable input of the succeeding counter if  
parallel clocking is used, or to the clock input The maximum / minimum count output can  
be used to accomplish look-ahead for high
Features  
Ordering Information  
e Code  
vious Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Pa
DILP-16
PRDP0016AE-B  
(DP-16FV)  
HD74LS190P  
HD74LS190FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (J)  
FP  
EL (2,000 pcs/reel)  
Notes: Please consult the sales office for the above package availability.  
Rev.3.00, Jul.15.2005, page 1 of 10  

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