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HD74LS191FP PDF预览

HD74LS191FP

更新时间: 2024-09-22 13:01:47
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器逻辑集成电路时钟
页数 文件大小 规格书
11页 93K
描述
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, FP-16DA

HD74LS191FP 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.3针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.47其他特性:TCO OUTPUT
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:10.06 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.008 A工作模式:SYNCHRONOUS
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):35 mA
传播延迟(tpd):36 ns认证状态:Not Qualified
座面最大高度:2.2 mm子类别:Counters
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.5 mm
最小 fmax:20 MHzBase Number Matches:1

HD74LS191FP 数据手册

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HD74LS191  
Synchronous Up / Down 4-bit Binary Counter (single clock line)  
REJ03D0453–0200  
Rev.2.00  
Feb.18.2005  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the steering logic. This mode  
of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The  
outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable  
input is high. The direction of the count is determined by the level of the down / up input. When low, the counter  
counts up and when high, it counts down. Level changes at the down / up input should be made only when the clock  
input is high. This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on  
the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs  
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by  
simply modifying the count length with the preset inputs. The clock, down / up, and load inputs are buffered to lower  
the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words.  
Two outputs have been made available to perform the cascading function; ripple clock and made available to perform  
the cascading function; ripple clock and maximum / minimum count. The latter output produces a high-level output  
pulse with a duration approximately equal to one complete cycles to the clock when the counter overflows or  
underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the  
clock input when an overflow or underflow condition exists.  
The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if  
parallel clocking is used, or to the clock input if parallel enabling is used. The maximum / minimum count output can  
be used to accomplish look-ahead for high-speed operation.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS191P  
HD74LS191FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Rev.2.00, Feb.18.2005, page 1 of 10  

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