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HD74LS192FPEL PDF预览

HD74LS192FPEL

更新时间: 2024-11-09 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器触发器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
11页 98K
描述
Synchronous Up / Down Decade Counter (dual clock lines)

HD74LS192FPEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.3针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7Is Samacsys:N
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDSO-G16长度:10.06 mm
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.008 A
工作模式:SYNCHRONOUS湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):34 mA
传播延迟(tpd):47 ns认证状态:Not Qualified
座面最大高度:2.2 mm子类别:Counters
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.5 mm
最小 fmax:25 MHzBase Number Matches:1

HD74LS192FPEL 数据手册

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HD74LS192  
Synchronous Up / Down Decade Counter (dual clock lines)  
REJ03D0454–0200  
Rev.2.00  
Feb.18.2005  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change  
coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output  
counting spikes which are normally associated with asynchronous (ripple clock) counters. The outputs of the four  
master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of  
counting is determined by which count input is pulsed while the other count input is high. This counter is fully  
programmable; that is, each output may be preset to either level by desired data at the data inputs while the load inputs  
is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the  
counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input  
has been provided which forces all outputs to the low level when a high level is applied. The clear function is  
independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements.  
This reduces the number of clock drivers, etc., required for long words. This counter was designed to be cascaded  
without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-and down-  
counting functions.  
The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly,  
the carry output produces a pulse equal in width to the count up input when an overflow condition exists.  
The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs  
respectively of .the succeeding counter.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS192P  
HD74LS192FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Rev.2.00, Feb.18.2005, page 1 of 10  

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