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HD74LS191P PDF预览

HD74LS191P

更新时间: 2024-09-22 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器触发器逻辑集成电路光电二极管输出元件时钟
页数 文件大小 规格书
11页 93K
描述
Synchronous Up / Down 4-bit Binary Counter (single clock line)

HD74LS191P 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIP包装说明:6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.24
Is Samacsys:N其他特性:TCO OUTPUT
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDIP-T16长度:19.2 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.008 A
工作模式:SYNCHRONOUS湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):35 mA传播延迟(tpd):36 ns
认证状态:Not Qualified座面最大高度:5.06 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL EXTENDED端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:20 MHz
Base Number Matches:1

HD74LS191P 数据手册

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HD74LS191  
Synchronous Up / Down 4-bit Binary Counter (single clock line)  
REJ03D0453–0200  
Rev.2.00  
Feb.18.2005  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the steering logic. This mode  
of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The  
outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable  
input is high. The direction of the count is determined by the level of the down / up input. When low, the counter  
counts up and when high, it counts down. Level changes at the down / up input should be made only when the clock  
input is high. This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on  
the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs  
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by  
simply modifying the count length with the preset inputs. The clock, down / up, and load inputs are buffered to lower  
the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words.  
Two outputs have been made available to perform the cascading function; ripple clock and made available to perform  
the cascading function; ripple clock and maximum / minimum count. The latter output produces a high-level output  
pulse with a duration approximately equal to one complete cycles to the clock when the counter overflows or  
underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the  
clock input when an overflow or underflow condition exists.  
The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if  
parallel clocking is used, or to the clock input if parallel enabling is used. The maximum / minimum count output can  
be used to accomplish look-ahead for high-speed operation.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS191P  
HD74LS191FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Rev.2.00, Feb.18.2005, page 1 of 10  

HD74LS191P 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS193N TI

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SN74LS191N TI

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