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HD74LS193RPEL PDF预览

HD74LS193RPEL

更新时间： 2024-09-23 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器时钟
页数 文件大小 规格书
12页 107K
描述
Synchronous Up / Down Decade Counter (dual clock lines)

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中文翻译

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HD74LS193RPEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.48计数方向：BIDIRECTIONAL
系列：LSJESD-30 代码：R-PDSO-G16
长度：9.9 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：25000000 Hz
最大I（ol）：0.008 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：75 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：34 mA传播延迟（tpd）：47 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Counters最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL EXTENDED端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.95 mm最小 fmax：25 MHz
Base Number Matches：1

HD74LS193RPEL 数据手册

 浏览型号HD74LS193RPEL的Datasheet PDF文件第2页浏览型号HD74LS193RPEL的Datasheet PDF文件第3页浏览型号HD74LS193RPEL的Datasheet PDF文件第4页浏览型号HD74LS193RPEL的Datasheet PDF文件第5页浏览型号HD74LS193RPEL的Datasheet PDF文件第6页浏览型号HD74LS193RPEL的Datasheet PDF文件第7页 
HD74LS193  
Synchronous Up / Down Decade Counter (dual clock lines)  
REJ03D0455–0200  
Rev.2.00  
Feb.18.2005  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change  
coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output  
counting spikes, which are normally associated with asynchronous (ripple clock) counters. The outputs of the four  
master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of  
counting is determined by which count input is pulsed while the other count input is high. This counter is fully  
programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the  
load inputs is low. The output will change to agree with the data inputs independently of the count pulses. This feature  
allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A  
clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function  
is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive  
requirements. This reduces the number of clock drivers, etc., required for long words. This counter was designed to be  
cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-  
and down-counting functions.  
The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly,  
the carry output produces a pulse equal in width to the count up input when an overflow condition exists.  
The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs  
respectively of .the succeeding counter.  
Features  
•
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS193P  
DILP-16 pin  
P
—
PRSP0016DH-B  
(FP-16DAV)  
HD74LS193FPEL  
HD74LS193RPEL  
SOP-16 pin (JEITA)  
SOP-16 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Rev.2.00, Feb.18.2005, page 1 of 11  
1234567...12

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HD74LS194AFP HITACHI

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HD74LS194AFPEL RENESAS

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HD74LS194AFP-EL HITACHI

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 		Parallel In Parallel Out, LS Series, 4-Bit, Bidirectional, True Output, TTL, PDSO16, EIAJ,
HD74LS194AP RENESAS

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HD74LS194AP-E RENESAS

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