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HD74LS195AP PDF预览

HD74LS195AP

更新时间: 2024-09-23 13:00:23
品牌 Logo 应用领域
瑞萨 - RENESAS 移位寄存器
页数 文件大小 规格书
8页 188K
描述
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HD74LS195AP 数据手册

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HD74LS195A  
4-bit Parallel-Access Shift Register  
REJ03D0457–0300  
Rev.3.00  
Jul.15.2005  
This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct  
overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of  
operation:  
Parallel (broadside) load  
Shift (in the direction QA toward QD)  
Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data  
is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During  
loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift / load control input is high.  
Serial data for this mode is entered at the J-K inputs. These inputs permit the firsage to perform as a J-K, D-, or T-  
type flip-flop as shown in the function table.  
Features  
Ordering Information  
Package Co
(Previou
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRSP
(FP
HD74LS195AFPEL  
SOP-16 pin (JEITA)  
EL (2,000 pcs/reel)  
Pin Arrangement  
C
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
ar  
Q
A
B
Q
A
B
K
A
B
C
D
Q
Q
Q
C
D
Outputs  
Q
C
D
Q
Q
Parallel  
Inputs  
QD  
C
QD  
CK  
Shift/Load  
D
Clock  
Shift/Load  
GND  
(Top view)  
Rev.3.00, Jul.15.2005, page 1 of 7  

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