HD74LS190RP

更新时间： 2024-09-22 13:08:19

品牌	Logo	应用领域
瑞萨 - RENESAS		计数器逻辑集成电路时钟
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11页	198K
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HD74LS190RP 数据手册

HD74LS190

Synchronous Up / Down Decade Counter (signal clock line)

REJ03D0452–0200

Rev.2.00

Jul.15.2005

Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident

with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes

normally associated with asynchronous (ripple clock) counters.

The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the

enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made

only when the clock input is high. The direction of the count is determined by the level of the down / up input. When

low, the counter counts up and when high, it counts down. Level changes at the down / up input should be made only

when the clock input is high. This counter is fully programmable; that is, the outputs may be preset to either level by

placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the

data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N

dividers by simply modifying the count length with the preset inputs. The clock, down / up, and load inputs are

buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc., required for long

parallel words.

Two outputs have been made available to perform the cascading function: ripple clock and maximum / minimum count.

The latter output produces a high-level output pulse with a duration approximately equal to one complete cycles to the

clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in

width to the low-level portion of the clock input when an overflow or underflow conditions exists.

The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if

parallel clocking is used, or to the clock input if parallel enabling is used. The maximum / minimum count output can

be used to accomplish look-ahead for high-speed operation.

Features

•

Ordering Information

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

HD74LS190P

HD74LS190FPEL

—

PRSP0016DH-B

(FP-16DAV)

SOP-16 pin (JEITA)

EL (2,000 pcs/reel)

Notes: Please consult the sales office for the above package availability.

Rev.3.00, Jul.15.2005, page 1 of 10

12 3 4 5 6 7...11

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与HD74LS190RP相关器件

型号	品牌	获取价格	描述	数据表
HD74LS190RP-EL	HITACHI	获取价格	Decade Counter, LS Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL
HD74LS191	HITACHI	获取价格	Synchronous Up/Down 4-bit Binary Counters(single clock line)
HD74LS191	RENESAS	获取价格	Synchronous Up / Down 4-bit Binary Counter (single clock line)
HD74LS191FP	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, FP-16DA
HD74LS191FP-E	RENESAS	获取价格	暂无描述
HD74LS191FPEL	RENESAS	获取价格	Synchronous Up / Down 4-bit Binary Counter (single clock line)
HD74LS191P	RENESAS	获取价格	Synchronous Up / Down 4-bit Binary Counter (single clock line)
HD74LS191P-E	RENESAS	获取价格	暂无描述
HD74LS191RP	HITACHI	获取价格	Binary Counter, LS Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL
HD74LS191RP	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, FP-16DN

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