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FQU7N10LTU PDF预览

FQU7N10LTU

更新时间: 2024-01-20 10:23:09
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
9页 547K
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FQU7N10LTU 数据手册

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December 2000  
TM  
QFET  
FQD7N10 / FQU7N10  
100V N-Channel MOSFET  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
5.8A, 100V, R  
= 0.35@V = 10 V  
DS(on) GS  
Low gate charge ( typical 5.8 nC)  
Low Crss ( typical 10 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
This advanced technology is especially tailored to minimize  
on-state  
resistance,  
provide  
superior  
switching  
performance, and withstand high energy pulse in the  
avalanche and commutation modes. These devices are  
well suited for low voltage applications such as audio  
amplifiers, high efficiency switching DC/DC converters, and  
DC motor control.  
D
!
D
"
! "  
"
"
!
G
I-PAK  
FQU Series  
D-PAK  
FQD Series  
G
S
G
D
!
S
S
Absolute Maximum Ratings  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
FQD7N10 / FQU7N10  
Units  
V
V
I
Drain-Source Voltage  
100  
5.8  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
3.67  
23.2  
± 25  
50  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
V
GSS  
AS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
5.8  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
2.5  
mJ  
V/ns  
W
AR  
dv/dt  
6.0  
Power Dissipation (T = 25°C) *  
2.5  
P
A
D
Power Dissipation (T = 25°C)  
25  
W
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.2  
W/°C  
°C  
T , T  
-55 to +150  
J
STG  
Maximum lead temperature for soldering purposes,  
1/8from case for 5 seconds  
T
300  
°C  
L
Thermal Characteristics  
Symbol  
Parameter  
Typ  
--  
Max  
5.0  
50  
Units  
°C/W  
°C/W  
°C/W  
R
R
R
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient *  
Thermal Resistance, Junction-to-Ambient  
θJC  
θJA  
θJA  
--  
--  
110  
* When mounted on the minimum pad size recommended (PCB Mount)  
©2000 Fairchild Semiconductor International  
Rev. A2, December 2000  

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