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FQU4P40TU PDF预览

FQU4P40TU

更新时间: 2024-11-23 13:07:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
9页 650K
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FQU4P40TU 数据手册

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August 2000  
TM  
QFET  
FQD4P40 / FQU4P40  
400V P-Channel MOSFET  
General Description  
Features  
These P-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for electronic lamp ballast based on complimentary  
half bridge.  
-2.7A, -400V, R  
= 3.1@V = -10 V  
DS(on) GS  
Low gate charge ( typical 18 nC)  
Low Crss ( typical 11 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
S
!
D
G!  
I-PAK  
FQU Series  
D-PAK  
FQD Series  
G
S
G
D
S
!
D
Absolute Maximum Ratings  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
FQD4P40 / FQU4P40  
Units  
V
V
I
Drain-Source Voltage  
-400  
-2.7  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
-1.71  
-10.8  
± 30  
260  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
V
GSS  
AS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
-2.7  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
5.0  
mJ  
V/ns  
W
AR  
dv/dt  
-4.5  
Power Dissipation (T = 25°C) *  
2.5  
P
A
D
Power Dissipation (T = 25°C)  
50  
W
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.4  
W/°C  
°C  
T , T  
-55 to +150  
J
STG  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8" from case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Typ  
--  
Max  
2.5  
50  
Units  
°C/W  
°C/W  
°C/W  
R
R
R
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient *  
Thermal Resistance, Junction-to-Ambient  
θJC  
θJA  
θJA  
--  
--  
110  
* When mounted on the minimum pad size recommended (PCB Mount)  
©2000 Fairchild Semiconductor International  
Rev. A, August 2000  

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