EDI2CG272128V
White Electronic Designs
ADVANCED*
2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM
DESCRIPTION
FEATURES
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2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
The EDI2CG272128VxxD1 is a Synchronous/Synchronous
Burst SRAM, 72 position DIMM (144 contacts) Module,
small outline. The Module contains four (4) Synchronous
Burst Ram Devices, packaged in the industry standard
JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/
Sync Burst, Flow-Through, with support for linear burst.
This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous
Only Mode, provides a high performance cost advantage
over BiCMOS aysnchronous device architectures.
Linear and Sequential Burst Support via MODE pin
Access Speed(s): TKHQV = 8.5, 9, 12, 15ns
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally Self-timed Write
Individual Bank Sleep Mode enables (ZZ1, ZZ2)
Gold Lead Finish
3.3V 1ꢀ0 Operation
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP# / ADV# High, which provides
for Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well
as an Asynchronous Output enable. This Module has
been defined for Quad Words in both Read and Write
Operations.
Common Data I/O
High Capacitance (3ꢀpf) drive, at rated Access Speed
Single Total Array Clock
Multiple Vcc and Gnd
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com