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EDI2CG272128V-D1 PDF预览

EDI2CG272128V-D1

更新时间: 2024-11-09 23:50:03
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
11页 173K
描述
SSRAM Modules

EDI2CG272128V-D1 数据手册

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EDI2CG272128V  
2x128Kx72, 3.3V Sync/Sync Burst Flow-Through  
FEATURES  
2x128Kx72 Synchronous, Synchronous Burst  
The EDI2CG272128VxxD1 is a Synchronous/Synchronous Burst  
SRAM, 72 position DIMM (144 contacts) Module, small outline.  
The Module contains four (4) Synchronous Burst Ram Devices,  
packaged in the industry standard JEDEC 14mmx20mm TQFP  
placed on a Multilayer FR4 Substrate. The module architecture is  
defined as a Sync/Sync Burst, Flow-Through, with support for  
either linear or sequential burst. This module provides High  
Performance, 2-1-1-1 accesses when used in Burst Mode, and  
used as a Synchronous Only Mode, provides a high performance  
cost advantage over BiCMOS aysnchronous device architectures.  
Flow-Through Architecture  
Linear and Sequential Burst Support via MODE pin  
Access Speed(s): TKHQV = 8.5, 9, 12, 15ns  
Clock Controlled Registered Bank Enables (E1, E2)  
Clock Controlled Registered Address  
Clock Controlled Registered Global Write (GW)  
Aysnchronous Output Enable (G)  
Internally Self-timed Write  
Synchronous Only operations are performed via strapping ADSC  
Low, and ADSP / ADV High, which provides for Ultra Fast Accesses  
in Read Mode while providing for internally self-timed Early  
Writes.  
Individual Bank Sleep Mode Enables (ZZ1, ZZ2)  
Gold Lead Finish  
Synchronous/Synchronous Burst operations are in relation to an  
externally supplied clock, Registered Address, Registered Global  
Write, Registered Enables as well as an Asynchronous Output  
enable. This Module has been defined for Quad Word access in  
both read and write operations.  
3.3V ±10% Operation  
Common Data I/O  
High Capacitance (30pF) Drive, at Rated Access Speed  
Single Total Array Clock  
Multiple Vcc and Gnd  
August 2000 Rev.0  
ECO#13088  
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com  

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