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DSP56001A

更新时间： 2024-11-23 23:49:15

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其他 - ETC		数字信号处理器
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DSP56001A 24-Bit Digital Signal Processor Data Sheet

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DSP56001A 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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DSP56001A/D, Rev. 1

DSP56001A

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24-BIT DIGITAL SIGNAL PROCESSOR

The DSP56001A is an MPU-style general purpose Digital Signal Processor (DSP) composed of an

efficient 24-bit DSP core, program and data memories, various peripherals, and support

circuitry. The DSP56000 core is fed by on-chip Program RAM, two independent data RAMs, and

two data ROMs containing sine, A-law, and µ-law tables. The DSP56001A contains a Serial

Communication Interface (SCI), a Synchronous Serial Interface (SSI), and a parallel Host Interface

(HI). This combination of features, illustrated in Figure 1, makes the DSP56001A a cost-effective,

high-performance solution for high-precision general purpose digital signal processing. The

DSP56001A is intended as a replacement for the DSP56001. The DSP56002 should be considered for

new designs.

16-bit Bus

24-bit Bus

Program

Memory

512 × 24 RAM

64 × 24 ROM

(boot)

X Data

Memory

256 × 24 RAM

256 × 24 ROM

(A-law/µ-law)

Y Data

Memory

256 × 24 RAM

256 × 24 ROM

(sine)

Sync.

Serial

Comm.

(SCI)

Host

Interface

(HI)

Serial

(SSI)

or I/O

External

Address

Bus

PAB

XAB

YAB

Address

Generation

Unit

24-bit

56000 DSP

Core

Switch

GDB

PDB

XDB

YDB

External

Data

Bus

Internal

Data

Bus

Data

Switch

Control

Bus

Control

Program

Data ALU

24 × 24 + 56 → 56-bit MAC

Two 56-bit Accumulators

Interrupt

Control

Decode

Address

Controller

Generator

Clock

Generator

Program Control Unit

AA0884

IRQ

Figure 1 DSP56001A Block Diagram

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