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DSP56001FC20

更新时间： 2024-02-10 10:52:49

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		微控制器和处理器外围集成电路数字信号处理器时钟
页数	文件大小	规格书
64页	843K
描述
24-Bit General Purpose Digital Signal Processor

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技术参数
数据手册

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DSP56001FC20 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	132
Reach Compliance Code：	unknown	风险等级：	5.42
地址总线宽度：	16	桶式移位器：	NO
边界扫描：	NO	最大时钟频率：	20 MHz
外部数据总线宽度：	24	格式：	FIXED POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	S-PQFP-G132
JESD-609代码：	e0	长度：	20 mm
低功率模式：	YES	端子数量：	132
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	HCMOS	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	20 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

DSP56001FC20 数据手册

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by DSP56001/D

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

24-Bit General Purpose

Digital Signal Processor

DSP56001

Pin Grid Array (PGA)

Available in an 88 pin ceramic

through-hole package.

Ceramic Quad Flat Pack (CQFP)

Available in a 132 pin, small footprint,

surface mount package.

The DSP56001 is a member of Motorola’s family of

HCMOS, low-power, general purpose Digital Signal

Processors. The DSP56001 features 512 words of full

speed, on-chip program RAM (PRAM) memory, two

256 word data RAMs, two preprogrammed data

ROMs, and special on-chip bootstrap hardware to per-

mit convenient loading of user programs into the pro-

gram RAM. It is an off-the-shelf part since the program

Plastic Quad Flat Pack (PQFP)

Available in a 132 pin, small footprint,

surface mount package.

memory is user programmable. The core of the processor consists of three execution units operating in parallel — the data ALU,

the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data

memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, com-

pact code, straightforward.

The high throughput of the DSP56001 makes it well-suited for communication, high-speed control, numeric processing, computer

and audio applications. The key features which facilitate this throughput are:

• Speed

At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute

a 1024 point complex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles).

• Precision

• Parallelism

The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results

held in the 56-bit accumulators can range over 336 dB.

The data ALU, address arithmetic units, and program controller operate in parallel so that an in-

struction prefetch, a 24x24-bit multiplication, a 56-bit addition, two data moves, and two address

pointer updates using one of three types of arithmetic (linear, modulo, or reverse carry) can be

executed in a single instruction cycle. This parallelism allows a four coefficient Infinite Impulse Re-

sponse (IIR) filter section to be executed in only four cycles, the theoretical minimum for a single

multiplier architecture.

• Integration

In addition to the three independent execution units, the DSP56001 has six on-chip memories,

three on-chip MCU style peripherals (Serial Communication Interface, Synchronous Serial Inter-

face, and Host Interface), a clock generator and seven buses (three address and four data), mak-

ing the overall system functionally complete and powerful, but also very low cost, low power, and

compact.

• Invisible Pipeline

• Instruction Set

The three-stage instruction pipeline is essentially invisible to the programmer thus allowing

straightforward program development in either assembly language or a high-level language such

as ANSI C.

The 62 instruction mnemonics are MCU-like making the transition from programming micropro-

cessors to programming the DSP56001 digital signal processor as easy as possible. The orthog-

onal syntax supports control of the parallel execution units. This syntax provides 12,808,830 dif-

ferent instruction variations using the 62 instruction mnemonics. The no-overhead DO instruction

and the REPEAT (REP) instruction make writing straight-line code obsolete.

• DSP56000/DSP56001

Compatibility

The DSP56001 is identical to the DSP56000 except that it has 512x24-bits of on-chip program

RAM instead of 3.75K of program ROM; a 32x24-bit bootstrap ROM for loading the program RAM

from either a byte-wide memory mapped ROM or via the Host Interface; and the on-chip X and Y

Data ROMs have been preprogrammed as positive Mu- and A-Law to linear expansion tables and

a full, four quadrant sine wave table, respectively.

• Low Power

As a CMOS part, the DSP56001 is inherently very low power; however, three other features can

reduce power consumption to an exceptionally low level.

— The WAIT instruction shuts off the clock in the central processor portion of the DSP56001.

— The STOP instruction halts the internal oscillator.

— Power increases linearly (approximately) with frequency; thus, reducing the clock frequency

reduces power consumption.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Rev. 3

May 4, 1998

MOTOROLA INC., 1992

12 3 4 5 6 7...64

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与DSP56001FC20相关器件

型号	品牌	获取价格	描述	数据表
DSP56001FC27	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001FC33	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001FE20	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001FE27	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001FE33	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001RC20	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001RC27	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56001RC33	MOTOROLA	获取价格	24-Bit General Purpose Digital Signal Processor
DSP56002	MOTOROLA	获取价格	24-bit Digital Signal Processor
DSP56002DS	ETC	获取价格	DSP56002 24- Bit Digital Signal Processor Data Sheet

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