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DSP56002PV66 PDF预览

DSP56002PV66

更新时间: 2024-11-01 22:40:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 微控制器和处理器外围集成电路数字信号处理器装置时钟
页数 文件大小 规格书
110页 662K
描述
24-BIT DIGITAL SIGNAL PROCESSOR

DSP56002PV66 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP144,.87SQ,20
针数:144Reach Compliance Code:unknown
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.45Is Samacsys:N
地址总线宽度:16桶式移位器:NO
位大小:24边界扫描:NO
最大时钟频率:66 MHz外部数据总线宽度:24
格式:FIXED POINT集成缓存:NO
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G144
JESD-609代码:e0长度:20 mm
低功率模式:NODMA 通道数量:
外部中断装置数量:3串行 I/O 数:2
端子数量:144计时器数量:1
片上数据RAM宽度:24片上程序ROM宽度:
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP144,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
RAM(字数):512座面最大高度:1.6 mm
子类别:Digital Signal Processors最大压摆率:130 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:20 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

DSP56002PV66 数据手册

 浏览型号DSP56002PV66的Datasheet PDF文件第2页浏览型号DSP56002PV66的Datasheet PDF文件第3页浏览型号DSP56002PV66的Datasheet PDF文件第4页浏览型号DSP56002PV66的Datasheet PDF文件第5页浏览型号DSP56002PV66的Datasheet PDF文件第6页浏览型号DSP56002PV66的Datasheet PDF文件第7页 
Order this document by:  
DSP56002/D, Rev. 3  
SEMICONDUCTOR TECHNICAL DATA  
DSP56002  
24-BIT DIGITAL SIGNAL PROCESSOR  
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an  
efficient 24-bit DSP core, program and data memories, various peripherals, and support  
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.  
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),  
parallel Host Interface (HI), Timer/ Event Counter, Phase Lock Loop (PLL), and an On-Chip  
Emulation (OnCE™) port. This combination of features, illustrated in Figure 1, makes the  
DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital  
signal processing.  
16-bit Bus  
24-bit Bus  
1
6
3
15  
Program  
Memory  
512 × 24 RAM  
64 × 24 ROM  
(boot)  
X Data  
Memory  
256 × 24 RAM  
256 × 24 ROM  
(A-law/ µ-law)  
24-bit  
Timer/  
Event  
Sync.  
Serial  
Comm.  
(SCI)  
Host  
Interface  
(HI)  
Y Data  
Memory  
256 × 24 RAM  
256 × 24 ROM  
(sine)  
Serial  
(SSI)  
or I/O  
Counter  
or I/O  
or I/O  
External  
Address  
Bus  
PAB  
Address  
16  
Address  
Generation  
Unit  
24-bit  
56000 DSP  
Core  
XAB  
YAB  
Switch  
GDB  
PDB  
XDB  
YDB  
External  
Data  
Bus  
Internal  
Data  
Bus  
Data  
24  
Switch  
Switch  
OnCE™  
Port  
Control  
10  
Bus  
Control  
Program  
Program  
Address  
Data ALU  
24 × 24 + 56 56-bit MAC  
Two 56-bit Accumulators  
Interrupt  
Control  
Decode  
Controller  
Generator  
Clock  
PLL  
Gen.  
Program Control Unit  
7
4
3
IRQ  
AA0604  
Figure 1 DSP56002 Block Diagram  
©1996 MOTOROLA, INC.  
 

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