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DSP56002

更新时间： 2024-02-21 17:04:14

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		数字信号处理器
页数	文件大小	规格书
3页	249K
描述
24-bit Digital Signal Processor

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DSP56002 数据手册

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DSP56002P/D

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR

PRODUCT INFORMATION

DSP56002

DSP56L002

Product Brief

24-bit Digital Signal Processor

The DSP56002 and the DSP56L002 are MPU-style general purpose Digital Signal Processors

(DSPs), composed of an efﬁcient 24-bit digital signal processor core, program and data memories,

various peripherals, and support circuitry. The 56000-Family-compatible DSP core is fed by on-

chip program RAM, two independent data RAMs, and two data ROMs with sine and A-law and

µ-law tables. The DSP56002/L002 contains a Serial Communication Interface (SCI), Synchronous

Serial Interface (SSI), parallel Host Interface (HI), Timer/Event Counter, Phase-Locked Loop

(PLL), and On-chip Emulation (OnCE™) port. This combination of features, illustrated in Figure 1,

makes the DSP56002/L002 a cost-effective, high-performance solution for high-precision general-

purpose digital signal processing.

16-bit Bus

24-bit Bus

24-bit

Sync.

Serial

Host

Program

Memory

X Data

Memory

Y Data

Memory

Timer /

Event

Serial

(SSI)

Comm. Interface

512 × 24 RAM

256 × 24 RAM

(SCI)

or I/O

(HI)

64 × 24 ROM

256 × 24 ROM

(boot)

(A-law / µ-law)

(sine)

Counter or I/O

or I/O

External

Address

Bus

Address

PAB

24-bit

56000 DSP

Core

Address

Generation

Unit

XAB

YAB

Switch

GDB

PDB

XDB

YDB

Internal

Data

External

Data

Bus

Switch

OnCE^TMPort

Control

Data ALU

Bus

Program

Decode

Program

Interrupt

Control

Address

24 × 24 + 56 → 56-bit MAC

Control

Controller

Generator

Clock

PLL

Two 56-bit Accumulators

Program Control Unit

Gen.

IRQ

Figure 1 DSP56002/L002 Block Diagram

Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA INC., 1994

For More Information On This Product,

Go to: www.freescale.com

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