Freescale Semiconductor, Inc.
MOTOROLA
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DSP56009/D, Rev. 1
SEMICONDUCTOR TECHNICAL DATA
DSP56009
SYMPHONY AUDIO DSP FAMILY
24-BIT DIGITAL SIGNAL PROCESSORS
Motorola designed the Symphony™ family of high-performance, programmable Digital Signal
Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,
Dolby AC-3 Surround, MPEG1 Layer 2, and Digital Theater Sound (DTS) processing. Software
for these applications is licensed by Motorola for integration into products like audio/ video
receivers, televisions, DVD applications, and automotive sound systems with such user-
developed features as digital equalization and sound field processing. The DSP56009 is an MPU-
style general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core,
program and data memories, various peripherals optimized for audio, and support circuitry. As
illustrated in Figure 1, the DSP56000 core family compatible DSP is fed by program memory,
two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host
Interface (SHI), External Memory Interface (EMI), dedicated I/ O lines, on-chip Phase Lock Loop
(PLL), and On-Chip Emulation (OnCE ) port. The DSP56009 has more on-chip memory than
the DSP56004 or DSP56007.
ˇ
16-Bit Bus
24-Bit Bus
4
9
5
29
General
Purpose
Input/
Serial
Serial
External
Audio
Interface
(SAI)
Host
Interface
(SHI)
Memory
Interface
(EMI)
X Data
Memory*
Program
Memory*
Y Data
Memory*
Output
PAB
Address
Generation
Unit
24-Bit
DSP56000
Core
XAB
YAB
GDB
PDB
XDB
YDB
Internal
Data
Bus
Switch
TM
OnCE Port
Program
Address
Generator
Program
Decode
Controller
Data ALU
24 × 24 + 56 → 56-Bit MAC
Two 56-Bit Accumulators
Interrupt
Control
Clock
PLL
Gen.
Program Control Unit
Refer to Table 1 for memory configurations.
4
*
3
4
IRQA, IRQB, NMI, RESET
AA0248
Figure 1 DSP56009 Block Diagram
©1996, 1997 MOTOROLA, INC.
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