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DSP56166

更新时间： 2024-11-23 22:40:39

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		数字信号处理器
页数	文件大小	规格书
63页	439K
描述
16-bit General Purpose Digital Signal Processor

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技术参数
数据手册

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DSP56166 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, QFP112,.91SQ	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.3	HTS代码：	8542.31.00.01
风险等级：	5.86	地址总线宽度：	16
桶式移位器：	NO	位大小：	16
边界扫描：	NO	最大时钟频率：	60 MHz
外部数据总线宽度：	16	格式：	FIXED POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	S-CQFP-G112
JESD-609代码：	e0	长度：	19.64 mm
低功率模式：	YES	端子数量：	112
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QFP
封装等效代码：	QFP112,.91SQ	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
RAM（字数）：	4096	座面最大高度：	3.45 mm
子类别：	Digital Signal Processors	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	HCMOS
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	19.64 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

DSP56166 数据手册

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by DSP56166/D

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

Advance Information

16-bit General Purpose

Digital Signal Processor

DSP56166

Ceramic Quad Flat Pack (CQFP)

Available in a 112 pin, small footprint,

surface mount package.

The DSP56166 is the second member of Motorola’s DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal

Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166 has a built-in Σ∆ codec and

phase locked loop (PLL). This MPU-style DSP also contains, memories, digital peripherals, and provides a cost effective, high per-

formance solution to many DSP applications. On-Chip Emulation (OnCE ) circuitry provides convenient and inexpensive debug fa-

cilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly

simplified by using the OnCE. The DSP56166 RAM based is an off the shelf part since there are no user programmable ROM’s on-

chip. The DSP56166 ROM based contains a 12K ROM (8Kx 16 program ROM and 4Kx16 data ROM).

The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an

instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56166. The MPU-style programming

model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and development tools

of the DSP56100 family, DSP56000 family, and DSP96002 are so similar that learning to design and program one greatly reduces

the time needed to learn the others.

DSP56166ROM Feature List

DSP56100 Family Features

• Up to 30 Million Instructions per Second (MIPS) at 60

MHz.– 33.3 ns Instruction cycle

• Three 16-bit internal data and three 16-bit internal

address buses

• Single-cycle 16 x 16-bit parallel Multiply-Accumulate

• 2 x 40-bit accumulators with extension byte

• Fractional and integer arithmetic with support for

multiprecision arithmetic

• Highly parallel instruction set with unique DSP

addressing modes

• Nested hardware DO loops including infinite loops and

DO zero loop

• Two instruction LMS adaptive filter loop

• Fast auto-return interrupts

• Individual programmable wait states on the external bus

for program, data, and peripheral memory spaces

• Off-chip memory-mapped peripheral space with

programmable access time and separate peripheral

enable pin

• On-chip memory-mapped peripheral registers

• Low Power Wait and Stop modes

• On-Chip Emulation (OnCE) for unobtrusive, processor

speed independent debugging

• Operating frequency down to DC

• 5V single power supply

• Three external interrupt request pins

• Low power (HCMOS)

DSP56166ROM On-chip Resources

• 4K x 16 on-chip data RAM

• 4K x 16 on-chip data ROM

– No off-chip components required

• 25 general purpose I/O pins

• 256 x 16 on-chip program RAM

• 8K x 16 on-chip program ROM

• One external 16-bit address bus

• One external 16-bit data bus

• On-chip, programmable PLL

• Byte-wide Host Interface with DMA support

• Two independent reduced synchronous serial

interfaces

• One 16-bit timer

• On-chip Σ∆ voice band codec (A/D-D/A)

• 112 pin quad flat pack packaging

– Internal voltage reference (2/5 of positive power

supply)

Operational Differences Of The ROM Based Part From The RAM Based Part

• XROM can only be accessed during a single read or the

first read of a dual parallel read instruction (see note on

page 2)

• Reset mode 1 vectors to P:$0100

• PROM area P:$2080 — P:$20FF is reserved and

should not be programmed or accessed by the user

This document contains information on a new product. Speciﬁcations and information herein are subject to change without notice.

MOTOROLA

MOTOROLA INC., 1993

6/15/93

12 3 4 5 6 7...63

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与DSP56166相关器件

型号	品牌	获取价格	描述	数据表
DSP56166ROM	MOTOROLA	获取价格	16-bit General Purpose Digital Signal Processor
DSP56200L10	ETC	获取价格	Digital Filter
DSP56200P	MOTOROLA	获取价格	Digital Filter, CMOS, PDIP28
DSP56300	MOTOROLA	获取价格	DSP56301 Digital Signal Processor
DSP56300	FREESCALE	获取价格	Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56300AD	MOTOROLA	获取价格	24-Bit Audio Digital Signal Processor
DSP56300FM	MOTOROLA	获取价格	24-Bit Audio Digital Signal Processor
DSP56300FM	FREESCALE	获取价格	24-Bit Audio Digital Signal Processor
DSP56300FM/AD	MOTOROLA	获取价格	high density CMOS device with 3.3 V inputs and outputs
DSP56300FM/AD	FREESCALE	获取价格	a high-density CMOS device

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