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DSP56156ROMFV60 PDF预览

DSP56156ROMFV60

更新时间： 2024-11-24 15:42:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路装置
页数 文件大小 规格书
76页 654K
描述
16-BIT, 60 MHz, OTHER DSP, PQFP112, 20 X 20 MM, 1.50 MM HEIGHT, PLASTIC, TQFP-112

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DSP56156ROMFV60 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：112
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.7
Is Samacsys：N其他特性：30 MIPS; EMULATION HARDWARE; 3 EXECUTION UNITS; 8-BIT HOST INTERFACE PORT
地址总线宽度：16桶式移位器：NO
边界扫描：NO最大时钟频率：60 MHz
外部数据总线宽度：16格式：FIXED POINT
集成缓存：NO内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G112长度：20 mm
低功率模式：YESDMA 通道数量：
外部中断装置数量：2串行 I/O 数：2
端子数量：112计时器数量：1
片上数据RAM宽度：16片上程序ROM宽度：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
认证状态：Not QualifiedRAM（字数）：2000
ROM可编程性：MROM座面最大高度：1.6 mm
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：HCMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：20 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

DSP56156ROMFV60 数据手册

 浏览型号DSP56156ROMFV60的Datasheet PDF文件第2页浏览型号DSP56156ROMFV60的Datasheet PDF文件第3页浏览型号DSP56156ROMFV60的Datasheet PDF文件第4页浏览型号DSP56156ROMFV60的Datasheet PDF文件第5页浏览型号DSP56156ROMFV60的Datasheet PDF文件第6页浏览型号DSP56156ROMFV60的Datasheet PDF文件第7页 
Order this document  
by DSP56156/D  
REV 1  
MOTOROLA  
SEMICONDUCTOR  
TECHNICAL DATA  
DSP56156  
DSP56156ROM  
Advance Information  
16-bit Digital Signal Processor  
The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi-  
conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro-  
gram and data memories, a number of peripherals, and system support circuitry. Unique features  
of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This com-  
bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP  
applications, especially speech coding, digital communications, and cellular base stations.  
The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100-  
based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to  
six operations to be performed during each instruction cycle. This parallelism greatly increases the  
effective processing speed of the DSP56156. The MPU-style programming model and instruction  
set allow straightforward generation of efficient, compact code. The basic architectures and devel-  
opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to  
design and program one greatly reduces the time needed to learn the others.  
On-Chip Emulation (OnCETM port) circuitry provides convenient and inexpensive debug facil-  
ities normally available only through expensive external hardware. Development costs are re-  
duced and in-field testing is greatly simplified using the OnCETM port. Figure 1 illustrates the  
DSP56156 in detail.  
16-bit Bus  
7
2
5
5
15  
Sigma-  
Delta  
16-bit  
Sync.  
Sync.  
Host  
Program  
Data  
Timer/  
Event  
Serial  
(SSI)  
or I/O  
Serial Interface  
Memory *  
Memory  
Codec  
(SSI)  
(HI)  
2048 × 16 RAM 2048 × 16 RAM  
Counter  
or I/O  
or I/O  
64 × 16 ROM  
(boot)  
External  
Address  
Bus  
PAB  
16-bit  
Address  
16  
Address  
XAB1  
XAB2  
Generation  
Unit  
56100 DSP  
Core  
Switch  
GDB  
PDB  
XDB  
Internal  
Data  
External  
Data  
Data  
16  
Bus  
Bus  
Switch  
Switch  
OnCE™ Port  
Clock  
Control  
9
Program  
Decode  
Program  
Data ALU  
16 x 16 + 40 —> 40-bit MAC  
Two 40-bit Accumulators  
Interrupt  
Control  
Bus  
Address  
Controller  
Generator  
Control  
PLL  
Gen.  
Program Control Unit  
3
4
IRQ  
2
* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM  
Figure 1 DSP56156 Block Diagram  
Specifications and information herein are subject to change without notice.  
OnCE is a trademark of Motorola, Inc.  
MOTOROLA INC., 1994  
1234567...76

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