Datasheet > DSP56301PW100

DSP56301PW100

更新时间： 2024-01-21 13:15:27

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		外围集成电路数字信号处理器时钟
页数	文件大小	规格书
124页	2296K
描述
24-Bit Digital Signal Processor

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数据手册

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DSP56301PW100 数据手册

DSP56301

Rev. 10, 7/2006

Freescale Semiconductor

Technical Data

DSP56301

24-Bit Digital Signal Processor

Memory Expansion Area

The DSP56301 is intended

for general-purpose digital

signal processing,

particularly in multimedia

and telecommunication

applications, such as video

conferencing and cellular

telephony.

Y Data

X Data

Program

RAM

Host

Interface

Triple

Timer

ESSI

SCI

RAM

2048 × 24

bits

RAM

2048 × 24

bits

4096 × 24 bits

(Default)

Peripheral

Expansion Area

External

Address

Bus

Address

Generator

Unit

Six-Channel

DMA Unit

XAB

PAB

DAB

Switch

External

Bus

24-Bit

DSP56300

Core

Interface

and

Boot-

strap

ROM

I-Cache

Control

DDB

YDB

XDB

PDB

GDB

External

Data

Bus

Internal

Data

Bus

What’s New?

Rev. 10 includes the following

changes:

Switch

•

Removes all references to

Motorola. No specifications or

part numbers were changed.

Power

EXTAL

XTAL

Management

Clock

Data ALU

Program

Decode

Program

→

24 × 24 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

Interrupt

Address

PLL

Controller

Generator

OnCE™

MODD/IRQD

MODC/IRQC

MODB/IRQB

MODA/IRQA

RESET

PINIT/NMI

Figure 1. DSP56301 Block Diagram

The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors

(DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural

features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The

DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family

offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling

wireless, telecommunications, and multimedia products.

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