Technical Data
DSP56305/D
Rev. 3, 1/2002
24-Bit Digital Signal
Processor
51
6
6
3
Memory Expansion Area
Program
Y Memory
X Memory*
Memory*
RAM
2 K × 24
RAM
6.5 K × 24
ROM
6 K × 24
Timer Host ESSI
SCI
FCOP VCOP CCOP
RAM
3.75 K × 24
ROM
3 K × 24
*default
*default
Peripheral
Expansion Area
Motorola designed
the DSP56305 to
deliver the high
performancerequired
to support Global
System for Mobile
(GSM)
YAB
External
24
Address
Generation
Unit
XAB
PAB
DAB
Address
Bus
Address
Switch
Six Channel
DMA Unit
External
Bus
24-Bit
15
Interface
&
DSP56300
Core
I-Cache
Control
Control
DDB
YDB
XDB
PDB
GDB
communications
applications that use
digital signal
24
Internal
Data
External
Data Bus
Switch
Bus
Data
Switch
processingto perform
channel equalization,
channel coding, and
speech coding.
Power
EXTAL
XTAL
Mngmnt
Clock
5
Data ALU
Generator
Program
Program
Decode
Program
Address
Generator
+
→
56-bit MAC
24 × 24 56
JTAG
Interrupt
Two 56-bit Accumulators
56-bit Barrel Shifter
PLL
Controller
Controller
OnCE™
DE
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
2
RESET
PINIT/NMI
Figure 1. DSP56305 Block Diagram
By combining three dedicated on-chip
hardware coprocessors (filter, Viterbi, and
cyclic code) with a DSP56300 core, the
DSP56305 performs all the complex signal
processing required by a single radio
frequency (RF) carrier in one chip, satisfying
the demand for high integration cost
effectively. The DSP56300 core includes an
on-chip PLL, a Data ALU, an instruction
cache, on-chip debugging modules, on-chip
program and data memory, six DMA
channels, and an external memory expansion
port. In addition to the coprocessors, the
DSP56305 provides two types of serial ports, a
PCI/Universal bus 32-bit host interface, and
timers (see Figure 1). The DSP56305 provides
an industry-leading performance rate of 100
MIPS at 3.3 V.