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DSP56303UMAD

更新时间： 2024-01-11 06:09:29

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DSP56303 Users Manual Addendum

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DSP56303UMAD 数据手册

Freescale Semiconductor, Inc.

Addendum

DSP56303UMAD/D

Rev. 1, 11/2002

DSP56303 User’s

Manual Addendum

CONTENTS

1 Introduction

Introduction...............1

Modified Signal

This document provides updated information for revision 1 of the DSP56303 User’s Manual

(DSP56303UM/D). The updates include the following:

Definitions.................1

Operating Mode

and Definition............2

Bus Control Register

(BCR) Layout and

• Modified signal definitions

• New Operating Mode Register (OMR) layout and bit definitions

• New Bus Control Register (BCR) layout and bit definitions

• Updated SCI Receive Register (SRX) Description

• Updated Programming sheets for the OMR, BCR, Address Attribute Registers (AAR[3–0]), and Timer

Registers (TLR, TCPR, TCR)

Definition...................3

SCI Receive Register

(SRX) Description .....3

Updated Programming

Sheets.........................3

2 Modified Signal Definitions

Area to Change

Change Description

Table 2-1, p. 2-1

•

For Notes 1–4, delete the last sentence in each note. All internal keepers are disabled and

do not affect device operation.

•

Change Ground (GND) to Ground (GND)⁵.

Change Note 5 to read as follows:

5. The number of Ground signals listed are for the 144-pin TQFP package.

For the 196-ball MAP-BGA package, there are 66 GND connections.

Figure 2-1, p. 2-2

Table 2-3, p. 2-4

•

In the figure, change Grounds: to Grounds :

At the bottom of the figure, add the following:

4. The GND signals are listed for the 144-pin TQFP package. For the 196-ball

MAP-BGA package, all grounds except GND and GND are connected together

and referenced as GND. There are 64 GND connections.

•

Change the note at the end of the table to the following:

Note:

The subsystem GND signals (GND , GND , GND , GND , GND , and

Q D C H

GND ) are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA

package, all grounds except GND and GND are connected together inside

the package and referenced as GND.

Table 2-8, pp. 2-7 to

2-8

•

Change BR signal State During Reset, Stop, or Wait to:

Reset: Output (deasserted)

State during Stop/Wait depends on BRH bit setting:

• BRH = 0: Output, deasserted

• BRH = 1: Maintains last state (that is, if asserted, remains asserted)

Change BB signal State During Reset, Stop, or Wait to Ignored input

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7 8

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与DSP56303UMAD相关器件

型号	品牌	获取价格	描述	数据表
DSP56303VF100	FREESCALE	获取价格	24-Bit Digital Signal Processor
DSP56303VF100R2	MOTOROLA	获取价格	24-BIT, 100MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196
DSP56303VL100	FREESCALE	获取价格	24-Bit Digital Signal Processor
DSP56303VL100R2	NXP	获取价格	24-BIT, 100 MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196
DSP56304GC66	ETC	获取价格	24-Bit Digital Signal Processor
DSP56304GC80	ETC	获取价格	24-Bit Digital Signal Processor
DSP56304PV66	ETC	获取价格	24-Bit Digital Signal Processor
DSP56304PV80	ETC	获取价格	24-Bit Digital Signal Processor
DSP56305DS	ETC	获取价格	DSP56305 Single Chip Channel Codec Digital Signal Processor Data Sheet
DSP56305VF100	ETC	获取价格	DSP\|24-BIT\|CMOS\|BGA\|252PIN\|PLASTIC

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