Freescale Semiconductor, Inc.
Technical Data
DSP56362/D
Rev. 3, 02/2004
24-Bit Audio Digital
Signal Processor
Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression
and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The
DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable
CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the
Motorola Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance
increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct
memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal
100 MHz clock at 3.3 V.
2
16
12
5
Program RAM/
Instruction
Cache
3072 × 24
Program ROM
30K × 24
Bootstrap ROM
X Data
RAM
5632 × 24
ROM
6144 × 24
Host
Interface
DAX
(SPDIF)
Triple
Timer
SHI
ESAI
Y Data
RAM
5632 × 24
ROM
6144 × 24
Memory
Expansion
Area
192 × 24
Peripheral
Expansion Area
YAB
18
Address
External
Address
Bus
XAB
PAB
DAB
Generation
Unit
Address
Switch
Six Channel
DMA Unit
DRAM/SRAM
Bus
24-Bit
DSP56300
Core
11
Interface
&
Control
I - Cache
Control
DDB
YDB
XDB
PDB
GDB
External
Data Bus
Switch
24
Internal
Data
Bus
Data
Switch
Power
EXTAL
Clock
Generator
Mngmnt.
Data ALU
6
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
+
→
56-bit MAC
24
×
24 56
JTAG
OnCE
Two 56-bit Accumulators
56-bit Barrel Shifter
PLL
CLKOUT
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
PINIT/NMI
AA0456G
Figure 1 DSP56362 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
IMOTOROLA
DSP56362 Advance Information
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