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DSP56005DS

更新时间： 2024-11-01 23:49:15
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其他 - ETC 数字信号处理器
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DSP56005 24-Bit Digital Signal Processor Datasheet

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DSP56005DS 数据手册

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Order this document  
by DSP56005/D  
Rev. 1  
Freescale Semiconductor, Inc.  
MOTOROLA  
SEMICONDUCTOR  
TECHNICAL DATA  
DSP56005  
Advance Information  
24-bit Digital Signal Processor  
The DSP56005 is an MPU-style general purpose Digital Signal Processor (DSP), composed of an  
efficient 24-bit digital signal processor core, program and data memories, various peripherals, and  
support circuitry. The 56000-Family-compatible DSP core is fed by a large program RAM, two in-  
dependent data RAMs, and two data ROMs with sine and arc-tangent tables. Like the DSP56002,  
the DSP56005 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),  
parallel Host Interface (HI), a 24-bit timer/ event counter, and On-Chip Emulation (OnCE ) port.  
Features of the DSP56005 include the large on-chip program memory, five Pulse Width Modula-  
tors (PWM), a watchdog timer, and an address decode pin for external peripherals. This combina-  
tion of features, illustrated in Figure 1, makes the DSP56005 a cost-effective, high-performance  
solution for many DSP and control applications, especially in high-performance motor control,  
optical disk drives and audio processing.  
16-bit Bus  
24-bit Bus  
14  
1
6
3
15  
Host  
Pulse  
24-bit  
Sync.  
Serial  
Program  
Memory  
X Data  
Memory  
Y Data  
Watch-  
dog  
Memory  
Interface  
(HI)  
Width  
Timer /  
Event  
Serial  
(SSI)  
or I/O  
Comm.  
(SCI)  
4608 × 24 RAM  
256 × 24 RAM  
256 × 24 RAM  
Modul.  
Timer  
96 × 24 ROM  
256 × 24 ROM  
256 × 24 ROM  
(5)  
(boot)  
(sine)  
(arc-tangent)  
or I/O  
Counter  
or I/O  
24-bit  
External  
Address  
Bus  
Address  
PAB  
Address  
16  
56000 DSP  
Core  
Generation  
Unit  
XAB  
YAB  
Switch  
GDB  
PDB  
XDB  
YDB  
Internal  
Data  
External  
Data  
Data  
24  
Bus  
Bus  
Switch  
Switch  
Control  
6
OnCE Port  
Data ALU  
Bus  
Program  
Decode  
Program  
Interrupt  
Control  
Address  
24 × 24 + 56 → 56-bit MAC  
Control  
Controller  
Generator  
Clock  
PLL  
Two 56-bit Accumulators  
Program Control Unit  
Gen.  
5
4
5
IRQ  
Figure 1 DSP56005 Block Diagram  
This document contains information on a product under development.  
Motorola reserves the right to change or discontinue this product without notice.  
MOTOROLA INC., 1995  
For More Information On This Product,  
Go to: www.freescale.com  
 
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