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DS90CR483VJD PDF预览

DS90CR483VJD

更新时间： 2024-11-06 20:08:51
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路驱动器
页数 文件大小 规格书
27页 1634K
描述
48-Bit Channel Link Serializer - 33-112MHz 100-TQFP -10 to 70

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中文翻译

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DS90CR483VJD 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.3Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：154558
Samacsys Pin Count：100Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Quad Flat PackagesSamacsys Footprint Name：NEZ (TQFP-100)
Samacsys Released Date：2015-04-16 09:48:08Is Samacsys：N
差分输出：YES驱动器位数：8
输入特性：STANDARD接口集成电路类型：LINE DRIVER
接口标准：EIA-644; TIA-644JESD-30 代码：S-PQFP-G100
JESD-609代码：e3长度：14 mm
湿度敏感等级：3功能数量：8
端子数量：100最高工作温度：70 °C
最低工作温度：-10 °C封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：97.4 ns
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED最大传输延迟：51.69 ns
宽度：14 mmBase Number Matches：1

DS90CR483VJD 数据手册

 浏览型号DS90CR483VJD的Datasheet PDF文件第2页浏览型号DS90CR483VJD的Datasheet PDF文件第3页浏览型号DS90CR483VJD的Datasheet PDF文件第4页浏览型号DS90CR483VJD的Datasheet PDF文件第5页浏览型号DS90CR483VJD的Datasheet PDF文件第6页浏览型号DS90CR483VJD的Datasheet PDF文件第7页 
DS90CR483, DS90CR484  
www.ti.com  
SNLS047H –FEBRUARY 2000–REVISED APRIL 2013  
DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz  
Check for Samples: DS90CR483, DS90CR484  
1
FEATURES  
DESCRIPTION  
The DS90CR483 transmitter converts 48 bits of  
CMOS/TTL data into eight LVDS (Low Voltage  
Differential Signaling) data streams. A phase-locked  
transmit clock is transmitted in parallel with the data  
streams over a ninth LVDS link. Every cycle of the  
transmit clock 48 bits of input data are sampled and  
transmitted. The DS90CR484 receiver converts the  
LVDS data streams back into 48 bits of CMOS/TTL  
data. At a transmit clock frequency of 112MHz, 48  
bits of TTL data are transmitted at a rate of 672Mbps  
per LVDS data channel. Using a 112MHz clock, the  
data throughput is 5.38Gbit/s (672Mbytes/s).  
2
•
Up to 5.38 Gbits/sec Bandwidth  
•
•
33 MHz to 112 MHz Input Clock Support  
LVDS SER/DES Reduces Cable and connector  
Size  
•
•
Pre-Emphasis Reduces Cable Loading Effects  
DC Balance Data Transmission Provided by  
Transmitter Reduces ISI Distortion  
•
Cable Deskew of +/−1 LVDS Data Bit Time (up  
to 80 MHz Clock Rate)  
•
•
•
•
•
5V Tolerant TxIN and Control Input Pins  
Flow Through Pinout for Easy PCB Design  
+3.3V Supply Voltage  
The multiplexing of data lines provides a substantial  
cable reduction. Long distance parallel single-ended  
buses typically require a ground wire per active signal  
(and have very limited noise rejection capability).  
Thus, for a 48-bit wide data and one clock, up to 98  
conductors are required. With this Channel Link  
chipset as few as 19 conductors (8 data pairs, 1 clock  
pair and a minimum of one ground) are needed. This  
provides an 80% reduction in cable width, which  
provides a system cost savings, reduces connector  
physical size and cost, and reduces shielding  
requirements due to the cables' smaller form factor.  
Transmitter Rejects Cycle-to-Cycle Jitter  
Conforms to ANSI/TIA/EIA-644-1995 LVDS  
Standard  
•
Both Devices are Available in 100 Lead TQFP  
Package  
The 48 CMOS/TTL inputs can support a variety of  
signal combinations. For example, 6 8-bit words or 5  
9-bit (byte + parity) and 3 controls.  
The DS90CR483/DS90CR484 chipset is improved  
over prior generations of Channel Link devices and  
offers higher bandwidth support and longer cable  
drive with three areas of enhancement. To increase  
bandwidth, the maximum clock rate is increased to  
112 MHz and  
8 serialized LVDS outputs are  
provided. Cable drive is enhanced with a user  
selectable pre-emphasis feature that provides  
additional output current during transitions to  
counteract cable loading effects. Optional DC  
balancing on a cycle-to-cycle basis, is also provided  
to reduce ISI (Inter-Symbol Interference). With pre-  
emphasis and DC balancing, a low distortion eye-  
pattern is provided at the receiver end of the cable. A  
cable deskew capability has been added to deskew  
long cables of pair-to-pair skew of up to +/−1 LVDS  
data bit time (up to 80 MHz Clock Rate). These three  
enhancements allow cables 5+ meters in length to be  
driven.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2013, Texas Instruments Incorporated  
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DS90CR483VJD 替代型号

型号 品牌 替代类型 描述 数据表
DS90CR483VJDX TI

类似代替

 48-Bit Channel Link Serializer - 33-112MHz 100-TQFP -10 to 70

与DS90CR483VJD相关器件

型号 品牌 获取价格 描述 数据表
DS90CR483VJDX TI

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 		48-Bit Channel Link Serializer - 33-112MHz 100-TQFP -10 to 70
DS90CR484 NSC

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 		48-Bit LVDS Channel Link Serializer/Deserializer
DS90CR484 TI

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 		48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR484A TI

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 		48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持
DS90CR484AVJD TI

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 		DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90CR484AVJD/NOPB TI

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 		48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持 |
DS90CR484AVJDX/NOPB TI

获取价格

 		48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持 |
DS90CR484SLB NSC

获取价格

 		IC LINE RECEIVER, QCC128, 0.50 MM PITCH, CSP-128, Line Driver or Receiver
DS90CR484SLB TI

获取价格

 		LINE RECEIVER, QCC128, 0.50 MM PITCH, CSP-128
DS90CR484VJD NSC

获取价格

 		48-Bit LVDS Channel Link Serializer/Deserializer

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