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DS90CR484VJD/NOPB PDF预览

DS90CR484VJD/NOPB

更新时间： 2024-11-09 20:06:15
品牌 Logo 应用领域
美国国家半导体 - NSC 接口集成电路
页数 文件大小 规格书
22页 480K
描述
IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver

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中文翻译

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DS90CR484VJD/NOPB 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TFQFP, TQFP100,.63SQReach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.43输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mm湿度敏感等级：2
功能数量：8端子数量：100
最高工作温度：70 °C最低工作温度：-10 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装等效代码：TQFP100,.63SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：97.4 ns接收器位数：8
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40最大传输延迟：51.69 ns
宽度：14 mmBase Number Matches：1

DS90CR484VJD/NOPB 数据手册

 浏览型号DS90CR484VJD/NOPB的Datasheet PDF文件第2页浏览型号DS90CR484VJD/NOPB的Datasheet PDF文件第3页浏览型号DS90CR484VJD/NOPB的Datasheet PDF文件第4页浏览型号DS90CR484VJD/NOPB的Datasheet PDF文件第5页浏览型号DS90CR484VJD/NOPB的Datasheet PDF文件第6页浏览型号DS90CR484VJD/NOPB的Datasheet PDF文件第7页 
March 2004  
DS90CR483 / DS90CR484  
48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz  
pre-emphasis feature that provides additional output current  
General Description  
during transitions to counteract cable loading effects. Op-  
The DS90CR483 transmitter converts 48 bits of CMOS/TTL  
tional DC balancing on a cycle-to-cycle basis, is also pro-  
data into eight LVDS (Low Voltage Differential Signaling)  
vided to reduce ISI (Inter-Symbol Interference). With pre-  
data streams. A phase-locked transmit clock is transmitted in  
emphasis and DC balancing, a low distortion eye-pattern is  
parallel with the data streams over a ninth LVDS link. Every  
provided at the receiver end of the cable. A cable deskew  
cycle of the transmit clock 48 bits of input data are sampled  
capability has been added to deskew long cables of pair-to-  
and transmitted. The DS90CR484 receiver converts the  
pair skew of up to +/−1 LVDS data bit time (up to 80 MHz  
LVDS data streams back into 48 bits of CMOS/TTL data. At  
Clock Rate). These three enhancements allow cables 5+  
a transmit clock frequency of 112MHz, 48 bits of TTL data  
meters in length to be driven.  
are transmitted at a rate of 672Mbps per LVDS data channel.  
The chipset is an ideal means to solve EMI and cable size  
Using a 112MHz clock, the data throughput is 5.38Gbit/s  
problems associated with wide, high speed TTL interfaces.  
(672Mbytes/s).  
For more details, please refer to the “Applications Informa-  
tion” section of this datasheet.  
The multiplexing of data lines provides a substantial cable  
reduction. Long distance parallel single-ended buses typi-  
cally require a ground wire per active signal (and have very  
limited noise rejection capability). Thus, for a 48-bit wide  
Features  
data and one clock, up to 98 conductors are required. With  
this Channel Link chipset as few as 19 conductors (8 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides an 80% reduction in cable width,  
which provides a system cost savings, reduces connector  
physical size and cost, and reduces shielding requirements  
due to the cables’ smaller form factor.  
n Up to 5.38 Gbits/sec bandwidth  
n 33 MHz to 112 MHz input clock support  
n LVDS SER/DES reduces cable and connector size  
n Pre-emphasis reduces cable loading effects  
n DC balance data transmission provided by transmitter  
reduces ISI distortion  
n Cable Deskew of +/−1 LVDS data bit time (up to 80  
MHz Clock Rate)  
n 5V Tolerant TxIN and control input pins  
n Flow through pinout for easy PCB design  
n +3.3V supply voltage  
The 48 CMOS/TTL inputs can support a variety of signal  
combinations. For example, 6 8-bit words or 5 9-bit (byte +  
parity) and 3 controls.  
The DS90CR483/DS90CR484 chipset is improved over prior  
generations of Channel Link devices and offers higher band-  
width support and longer cable drive with three areas of  
enhancement. To increase bandwidth, the maximum clock  
rate is increased to 112 MHz and 8 serialized LVDS outputs  
are provided. Cable drive is enhanced with a user selectable  
n Transmitter rejects cycle-to-cycle jitter  
n Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard  
n Both devices are available in 100 lead TQFP package  
Generalized Block Diagrams  
10091801  
© 2004 National Semiconductor Corporation  
DS100918  
www.national.com  
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中文翻译

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DS90CR484VJD/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90CR484VJD/NOPB TI

功能相似

 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR484VJD NSC

功能相似

 48-Bit LVDS Channel Link Serializer/Deserializer

与DS90CR484VJD/NOPB相关器件

型号 品牌 获取价格 描述 数据表
DS90CR484VJDX TI

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 		OCTAL LINE RECEIVER, PQFP100, TQFP-100
DS90CR484VJDX/NOPB NSC

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 		IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR484VJDX/NOPB TI

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 		48-Bit Channel Link Deserializer - 33-112MHz 100-TQFP
DS90CR485 NSC

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 		133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485 TI

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 		133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485_15 TI

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 		133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485VS NSC

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 		133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485VS/NOPB NSC

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 		IC OCTAL LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR485VS/NOPB TI

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 		133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485VSX NSC

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 		IC OCTAL LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver

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