Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90CR484VJD

DS90CR484VJD

更新时间： 2024-11-05 22:16:59

品牌	Logo	应用领域
美国国家半导体 - NSC		接口集成电路
页数	文件大小	规格书
17页	352K
描述
48-Bit LVDS Channel Link Serializer/Deserializer

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数据手册
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DS90CR484VJD 数据手册

February 2000

DS90CR483 / DS90CR484

48-Bit LVDS Channel Link Serializer/Deserializer

provided. Cable drive is enhanced with a user selectable

pre-emphasis feature that provides additional output current

during transitions to counteract cable loading effects. DC

balancing on a cycle-to-cycle basis, is also provided to re-

duce ISI (Inter-Symbol Interference). With pre-emphasis and

DC balancing, a low distortion eye-pattern is provided at the

receiver end of the cable. A cable deskew capability has

been added to deskew long cables of pair-to-pair skew of up

to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These

three enhancements allow cables 5+ meters in length to be

driven.

General Description

The DS90CR483 transmitter converts 48 bits of CMOS/TTL

data into eight LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a ninth LVDS link. Every

cycle of the transmit clock 48 bits of input data are sampled

and transmitted. The DS90CR484 receiver converts the

LVDS data streams back into 48 bits of CMOS/TTL data. At

a transmit clock frequency of 112MHz, 48 bits of TTL data

are transmitted at a rate of 672Mbps per LVDS data channel.

Using a 112MHz clock, the data throughput is 5.38Gbit/s

(672Mbytes/s).

The chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

The multiplexing of data lines provides a substantial cable

reduction. Long distance parallel single-ended buses typi-

cally require a ground wire per active signal (and have very

limited noise rejection capability). Thus, for a 48-bit wide

data and one clock, up to 98 conductors are required. With

this Channel Link chipset as few as 19 conductors (8 data

pairs, 1 clock pair and a minimum of one ground) are

needed. This provides an 80% reduction in cable width,

which provides a system cost savings, reduces connector

physical size and cost, and reduces shielding requirements

due to the cables’ smaller form factor.

For more details, please refer to the “Applications Informa-

tion” section of this datasheet.

Features

n Up to 5.38 Gbits/sec bandwidth

n 33 MHz to 112 MHz input clock support

n LVDS SER/DES reduces cable and connector size

n Pre-emphasis reduces cable loading effects

n DC balance data transmission provided by transmitter

reduces ISI distortion

n Cable Deskew of +/−1 LVDS data bit time (up to 80

MHz Clock Rate)

n 5V Tolerant TxIN and control input pins

n Flow through pinout for easy PCB design

n +3.3V supply voltage

The 48 CMOS/TTL inputs can support a variety of signal

combinations. For example, 6 8-bit words or 5 9-bit (byte +

parity) and 3 controls.

The DS90CR483/DS90CR484 chipset is improved over prior

generations of Channel Link devices and offers higher band-

width support and longer cable drive with three areas of en-

hancement. To increase bandwidth, the maximum clock rate

is increased to 112 MHz and 8 serialized LVDS outputs are

n Transmitter rejects cycle-to-cycle jitter

n Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard

Generalized Block Diagrams

DS100918-1

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100918

www.national.com

12 3 4 5 6 7...17

中文翻译

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DS90CR484VJD 替代型号

型号	品牌	替代类型	描述	数据表
DS90CR484VJD/NOPB	TI	功能相似	48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR484VJD/NOPB	NSC	功能相似	IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver

与DS90CR484VJD相关器件

型号	品牌	获取价格	描述	数据表
DS90CR484VJD/NOPB	NSC	获取价格	IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR484VJD/NOPB	TI	获取价格	48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR484VJDX	TI	获取价格	OCTAL LINE RECEIVER, PQFP100, TQFP-100
DS90CR484VJDX/NOPB	NSC	获取价格	IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR484VJDX/NOPB	TI	获取价格	48-Bit Channel Link Deserializer - 33-112MHz 100-TQFP
DS90CR485	NSC	获取价格	133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485	TI	获取价格	133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485_15	TI	获取价格	133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485VS	NSC	获取价格	133MHz 48-bit Channel Link Serializer (6.384 Gbps)
DS90CR485VS/NOPB	NSC	获取价格	IC OCTAL LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver

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