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DS90CR486

更新时间： 2024-11-08 22:50:51

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
15页	348K
描述
133MHz 48-Bit Channel Lick Deserializer (6.384 Gbps)

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DS90CR486 数据手册

March 2003

DS90CR486

133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

cable deskew capability has been added to deskew long

General Description

cables of pair-to-pair skew. These three enhancements allow

The DS90CR486 receiver converts eight Low Voltage Differ-

long cables to be driven.

ential Signaling (LVDS) data streams back into 48 bits of

The DS90CR486 is intended to be used with the

LVCMOS/LVTTL data. Using a 133MHz clock, the data

DS90CR485 Channel Link Serializer. It is also backward

throughput is 6.384Gbit/s (798Mbytes/s).

compatible with serializers DS90CR481 and DS90CR483.

The multiplexing of data lines provides a substantial cable

The DS90CR486 is footprint compatible with the

reduction. Long distance parallel single-ended buses typi-

DS90CR484.

cally require a ground wire per active signal (and have very

The chipset is an ideal solution to solve EMI and intercon-

limited noise rejection capability). Thus, for a 48-bit wide

nect size problems for high-throughput point-to-point appli-

data and one clock, up to 98 conductors are required. With

cations.

this Channel Link chipset as few as 19 conductors (8 data

For more details, please refer to the “Applications Informa-

tion” section of this datasheet.

pairs, 1 clock pair and a minimum of one ground) are

needed. This provides an 80% reduction in interconnect

width, which provides a system cost savings, reduces con-

nector physical size and cost, and reduces shielding require-

ments due to the cables’ smaller form factor.

Features

n Up to 6.384 Gbps throughput

The DS90CR486 deserializer is improved over prior genera-

tions of Channel Link devices and offers higher bandwidth

support and longer cable drive with three areas of enhance-

ment. To increase bandwidth, the maximum clock rate is

increased to 133 MHz and 8 serialized LVDS outputs are

provided. Cable drive is enhanced with a user selectable

pre-emphasis (on DS90CR485) feature that provides addi-

tional output current during transitions to counteract cable

loading effects. Optional DC balancing on a cycle-to-cycle

basis, is also provided to reduce ISI (Inter-Symbol Interfer-

ence). With pre-emphasis and DC balancing, a low distortion

eye-pattern is provided at the receiver end of the cable. A

n 66MHz to 133MHz input clock support

n Reduces cable and connector size and cost

n Cable Deskew function

n DC balance reduces ISI distortion

n For point-to-point backplane or cable applications

n Low power, 890 mW typ at 133MHz

n Flow through pinout for easy PCB design

n +3.3V supply voltage

n 100-pin TQFP package

n Conforms to TIA/EIA-644-A-2001 LVDS Standard

Generalized Block Diagram

20025203

DS200252

www.national.com

12 3 4 5 6 7...15

中文翻译

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与DS90CR486相关器件

型号	品牌	获取价格	描述	数据表
DS90CR486_06	NSC	获取价格	133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
DS90CR486VS	NSC	获取价格	133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
DS90CR486VS/NOPB	TI	获取价格	133MHz 48 位 Channel Link 解串器 \| NEZ \| 100 \| -1
DS90CR486VSX/NOPB	TI	获取价格	133MHz 48 位 Channel Link 解串器 \| NEZ \| 100 \| -1
DS90CR486VSX/NOPB	NSC	获取价格	IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR561	NSC	获取价格	LVDS 18-Bit Color Flat Panel Display (FPD) Link
DS90CR561MDC	NSC	获取价格	暂无描述
DS90CR561MTD	NSC	获取价格	LVDS 18-Bit Color Flat Panel Display (FPD) Link
DS90CR561MTD/NOPB	TI	获取价格	LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR561MTDX	TI	获取价格	LINE DRIVER, PDSO48, LOW PROFILE, PLASTIC, TSSOP-48

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