Datasheet > DS90CR484AVJD/NOPB

DS90CR484AVJD/NOPB

更新时间： 2024-11-20 11:09:43

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
28页	1225K
描述
48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持 \| NEZ \| 100 \| -10 to 70

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

DS90CR484AVJD/NOPB 数据手册

浏览型号DS90CR484AVJD/NOPB的Datasheet PDF文件第2页

浏览型号DS90CR484AVJD/NOPB的Datasheet PDF文件第3页

浏览型号DS90CR484AVJD/NOPB的Datasheet PDF文件第4页

浏览型号DS90CR484AVJD/NOPB的Datasheet PDF文件第5页

浏览型号DS90CR484AVJD/NOPB的Datasheet PDF文件第6页

浏览型号DS90CR484AVJD/NOPB的Datasheet PDF文件第7页

DS90CR483A, DS90CR484A

www.ti.com

SNLS291A –APRIL 2008–REVISED APRIL 2013

DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz

Check for Samples: DS90CR483A, DS90CR484A

The multiplexing of data lines provides a substantial

FEATURES

cable reduction. Long distance parallel single-ended

buses typically require a ground wire per active signal

(and have very limited noise rejection capability).

Thus, for a 48-bit wide data and one clock, up to 98

conductors are required. With this Channel Link

chipset as few as 19 conductors (8 data pairs, 1 clock

pair and a minimum of one ground) are needed. This

provides an 80% reduction in cable width, which

provides a system cost savings, reduces connector

physical size and cost, and reduces shielding

requirements due to the cables' smaller form factor.

•

Up to 5.38 Gbits/sec Bandwidth

•

33 MHz to 112 MHz Input Clock Support

LVDS SER/DES Reduces Cable and Connector

Size

•

Pre-emphasis Reduces Cable Loading Effects

DC Balance Data Transmission Provided by

Transmitter Reduces ISI Distortion

•

Cable Deskew of +/−1 LVDS Data Bit Time (up

to 80 MHz Clock Rate)

The 48 CMOS/TTL inputs can support a variety of

signal combinations. For example, 6 8-bit words or 5

9-bit (byte + parity) and 3 controls.

•

5V Tolerant TxIN and Control Input Pins

Flow Through Pinout for Easy PCB Design

+3.3V Supply Voltage

The DS90CR483A/DS90CR484A chipset is improved

over prior generations of Channel Link devices and

offers higher bandwidth support and longer cable

drive with three areas of enhancement. To increase

bandwidth, the maximum clock rate is increased to

Transmitter Rejects Cycle-to-Cycle Jitter

Conforms to ANSI/TIA/EIA-644-1995 LVDS

Standard

•

Both Devices are Available in 100 Lead TQFP

Package

112 MHz and

8 serialized LVDS outputs are

provided. Cable drive is enhanced with a user

selectable pre-emphasis feature that provides

additional output current during transitions to

counteract cable loading effects. Optional DC

balancing on a cycle-to-cycle basis, is also provided

to reduce ISI (Inter-Symbol Interference). With pre-

emphasis and DC balancing, a low distortion eye-

pattern is provided at the receiver end of the cable. A

cable deskew capability has been added to deskew

long cables of pair-to-pair skew of up to +/−1 LVDS

data bit time (up to 80 MHz Clock Rate). These three

enhancements allow cables 5+ meters in length to be

driven.

DESCRIPTION

The DS90CR483A transmitter converts 48 bits of

CMOS/TTL data into eight LVDS (Low Voltage

Differential Signaling) data streams. A phase-locked

transmit clock is transmitted in parallel with the data

streams over a ninth LVDS link. Every cycle of the

transmit clock 48 bits of input data are sampled and

transmitted. The DS90CR484A receiver converts the

LVDS data streams back into 48 bits of CMOS/TTL

data. At a transmit clock frequency of 112MHz, 48

bits of TTL data are transmitted at a rate of 672Mbps

per LVDS data channel. Using a 112MHz clock, the

data throughput is 5.38Gbit/s (672Mbytes/s).

The chipset is an ideal means to solve EMI and cable

size problems associated with wide, high speed TTL

interfaces.

For more details, please refer to the Applications

Information section of this datasheet.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...28

中文翻译

下载PDF

DS90CR484AVJD/NOPB 替代型号

型号	品牌	替代类型	描述	数据表
DS90CR484AVJDX/NOPB	TI	完全替代	48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持 \|
DS90CR484AVJD	TI	完全替代	DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90CR484VJD/NOPB	TI	类似代替	48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

与DS90CR484AVJD/NOPB相关器件

型号	品牌	获取价格	描述	数据表
DS90CR484AVJDX/NOPB	TI	获取价格	48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持 \|
DS90CR484SLB	NSC	获取价格	IC LINE RECEIVER, QCC128, 0.50 MM PITCH, CSP-128, Line Driver or Receiver
DS90CR484SLB	TI	获取价格	LINE RECEIVER, QCC128, 0.50 MM PITCH, CSP-128
DS90CR484VJD	NSC	获取价格	48-Bit LVDS Channel Link Serializer/Deserializer
DS90CR484VJD/NOPB	NSC	获取价格	IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR484VJD/NOPB	TI	获取价格	48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR484VJDX	TI	获取价格	OCTAL LINE RECEIVER, PQFP100, TQFP-100
DS90CR484VJDX/NOPB	NSC	获取价格	IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR484VJDX/NOPB	TI	获取价格	48-Bit Channel Link Deserializer - 33-112MHz 100-TQFP
DS90CR485	NSC	获取价格	133MHz 48-bit Channel Link Serializer (6.384 Gbps)

与DS90CR484AVJD/NOPB相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90CR484AVJD/NOPB

DS90CR484AVJD/NOPB 数据手册

DS90CR484AVJD/NOPB 替代型号

与DS90CR484AVJD/NOPB相关器件

与DS90CR484AVJD/NOPB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90CR484AVJD/NOPB

DS90CR484AVJD/NOPB 数据手册

DS90CR484AVJD/NOPB 替代型号

与DS90CR484AVJD/NOPB相关器件

与DS90CR484AVJD/NOPB相关文章

您还可以找

您在本页遇到什么问题？