DS90CR481, DS90CR482
www.ti.com
SNLS137D –NOVEMBER 2000–REVISED APRIL 2013
DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz
Check for Samples: DS90CR481, DS90CR482
The multiplexing of data lines provides a substantial
1
FEATURES
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This
provides an 80% reduction in cable width, which
provides a system cost savings, reduces connector
physical size and cost, and reduces shielding
requirements due to the cables' smaller form factor.
2
•
3.168 Gbits/sec Bandwidth with 66 MHz Clock
5.376 Gbits/sec Bandwidth with 112 MHz Clock
65 - 112 MHz Input Clock Support
•
•
•
LVDS SER/DES Reduces Cable and Connector
Size
•
•
Pre-Emphasis Reduces Cable Loading Effects
Optional DC Balance Encoding Reduces ISI
Distortion
•
Cable Deskew of +/−1 LVDS Data Bit Time (up
The 48 CMOS/TTL inputs can support a variety of
signal combinations. For example, 6 8-bit words or 5
9-bit (byte + parity) and 3 controls.
to 80 MHz Clock Rate)
•
•
•
•
•
5V Tolerant TxIN and Control Input Pins
Flow Through Pinout for Easy PCB Design
+3.3V Supply Voltage
The DS90CR481/DS90CR482 chipset is improved
over prior generations of Channel Link devices and
offers higher bandwidth support and longer cable
drive with three areas of enhancement. To increase
bandwidth, the maximum clock rate is increased to
Transmitter Rejects Cycle-to-Cycle Jitter
Conforms to ANSI/TIA/EIA-644-1995 LVDS
Standard
112 MHz and
8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user
selectable pre-emphasis feature that provides
additional output current during transitions to
counteract cable loading effects. Optional DC
balancing on a cycle-to-cycle basis, is also provided
to reduce ISI (Inter-Symbol Interference). With pre-
emphasis and DC balancing, a low distortion eye-
pattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew
long cables of pair-to-pair skew of up to +/−1 LVDS
data bit time (up to 80 MHz Clock Rate). These three
enhancements allow cables 5+ meters in length to be
driven.
DESCRIPTION
The DS90CR481 transmitter converts 48 bits of
CMOS/TTL data into eight LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a ninth LVDS link. Every cycle of the
transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR482 receiver converts the
LVDS data streams back into 48 bits of
LVCMOS/TTL data. At a transmit clock frequency of
112MHz, 48 bits of TTL data are transmitted at a rate
of 672Mbps per LVDS data channel. Using a 112MHz
clock,
the
data
throughput
is
5.38Gbit/s
The chipset is an ideal means to solve EMI and cable
size problems associated with wide, high speed TTL
interfaces.
(672Mbytes/s). At a transmit clock frequency of
112MHz, 48 bits of TTL data are transmitted at a rate
of 672Mbps per LVDS data channel. Using a 66MHz
clock, the data throughput is 3.168Gbit/s
(396Mbytes/s).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
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