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DS90CR482VS/NOPB PDF预览

DS90CR482VS/NOPB

更新时间： 2024-11-24 11:11:47
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
26页 1242K
描述
48 位 LVDS 频道链接解串器 - 65 - 112MHz | NEZ | 100 | -10 to 70

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中文翻译

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DS90CR482VS/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP, TQFP100,.63SQ针数：100
Reach Compliance Code：compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.11差分输出：NO
高电平输入电流最大值：0.000015 A输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：S-PQFP-G100JESD-609代码：e4
长度：14 mm湿度敏感等级：3
功能数量：8端子数量：100
最高工作温度：70 °C最低工作温度：-10 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装等效代码：TQFP100,.63SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：接收器位数：9
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：280 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

DS90CR482VS/NOPB 数据手册

 浏览型号DS90CR482VS/NOPB的Datasheet PDF文件第2页浏览型号DS90CR482VS/NOPB的Datasheet PDF文件第3页浏览型号DS90CR482VS/NOPB的Datasheet PDF文件第4页浏览型号DS90CR482VS/NOPB的Datasheet PDF文件第5页浏览型号DS90CR482VS/NOPB的Datasheet PDF文件第6页浏览型号DS90CR482VS/NOPB的Datasheet PDF文件第7页 
DS90CR481, DS90CR482  
www.ti.com  
SNLS137D –NOVEMBER 2000–REVISED APRIL 2013  
DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz  
Check for Samples: DS90CR481, DS90CR482  
The multiplexing of data lines provides a substantial  
1
FEATURES  
cable reduction. Long distance parallel single-ended  
buses typically require a ground wire per active signal  
(and have very limited noise rejection capability).  
Thus, for a 48-bit wide data and one clock, up to 98  
conductors are required. With this Channel Link  
chipset as few as 19 conductors (8 data pairs, 1 clock  
pair and a minimum of one ground) are needed. This  
provides an 80% reduction in cable width, which  
provides a system cost savings, reduces connector  
physical size and cost, and reduces shielding  
requirements due to the cables' smaller form factor.  
2
•
3.168 Gbits/sec Bandwidth with 66 MHz Clock  
5.376 Gbits/sec Bandwidth with 112 MHz Clock  
65 - 112 MHz Input Clock Support  
•
•
•
LVDS SER/DES Reduces Cable and Connector  
Size  
•
•
Pre-Emphasis Reduces Cable Loading Effects  
Optional DC Balance Encoding Reduces ISI  
Distortion  
•
Cable Deskew of +/−1 LVDS Data Bit Time (up  
The 48 CMOS/TTL inputs can support a variety of  
signal combinations. For example, 6 8-bit words or 5  
9-bit (byte + parity) and 3 controls.  
to 80 MHz Clock Rate)  
•
•
•
•
•
5V Tolerant TxIN and Control Input Pins  
Flow Through Pinout for Easy PCB Design  
+3.3V Supply Voltage  
The DS90CR481/DS90CR482 chipset is improved  
over prior generations of Channel Link devices and  
offers higher bandwidth support and longer cable  
drive with three areas of enhancement. To increase  
bandwidth, the maximum clock rate is increased to  
Transmitter Rejects Cycle-to-Cycle Jitter  
Conforms to ANSI/TIA/EIA-644-1995 LVDS  
Standard  
112 MHz and  
8 serialized LVDS outputs are  
provided. Cable drive is enhanced with a user  
selectable pre-emphasis feature that provides  
additional output current during transitions to  
counteract cable loading effects. Optional DC  
balancing on a cycle-to-cycle basis, is also provided  
to reduce ISI (Inter-Symbol Interference). With pre-  
emphasis and DC balancing, a low distortion eye-  
pattern is provided at the receiver end of the cable. A  
cable deskew capability has been added to deskew  
long cables of pair-to-pair skew of up to +/−1 LVDS  
data bit time (up to 80 MHz Clock Rate). These three  
enhancements allow cables 5+ meters in length to be  
driven.  
DESCRIPTION  
The DS90CR481 transmitter converts 48 bits of  
CMOS/TTL data into eight LVDS (Low Voltage  
Differential Signaling) data streams. A phase-locked  
transmit clock is transmitted in parallel with the data  
streams over a ninth LVDS link. Every cycle of the  
transmit clock 48 bits of input data are sampled and  
transmitted. The DS90CR482 receiver converts the  
LVDS data streams back into 48 bits of  
LVCMOS/TTL data. At a transmit clock frequency of  
112MHz, 48 bits of TTL data are transmitted at a rate  
of 672Mbps per LVDS data channel. Using a 112MHz  
clock,  
the  
data  
throughput  
is  
5.38Gbit/s  
The chipset is an ideal means to solve EMI and cable  
size problems associated with wide, high speed TTL  
interfaces.  
(672Mbytes/s). At a transmit clock frequency of  
112MHz, 48 bits of TTL data are transmitted at a rate  
of 672Mbps per LVDS data channel. Using a 66MHz  
clock, the data throughput is 3.168Gbit/s  
(396Mbytes/s).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2013, Texas Instruments Incorporated  
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中文翻译

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DS90CR482VS/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90CR482VSX/NOPB TI

类似代替

 48 位 LVDS 频道链接解串器 - 65 - 112MHz | NEZ | 100 |
DS90CR482VS NSC

功能相似

 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

与DS90CR482VS/NOPB相关器件

型号 品牌 获取价格 描述 数据表
DS90CR482VSX NSC

获取价格

 		IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR482VSX/NOPB NSC

获取价格

 		IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CR482VSX/NOPB TI

获取价格

 		48 位 LVDS 频道链接解串器 - 65 - 112MHz | NEZ | 100 |
DS90CR483 NSC

获取价格

 		48-Bit LVDS Channel Link Serializer/Deserializer
DS90CR483 TI

获取价格

 		48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR483_04 NSC

获取价格

 		48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR483A TI

获取价格

 		DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90CR483AVJD TI

获取价格

 		DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90CR483AVJD/NOPB TI

获取价格

 		48-bit LVDS channel link serializer with input clock support from 33 MHz to 112 MHz 100-TQ
DS90CR483AVJDX/NOPB TI

获取价格

 		48 位 LVDS 通道链接串行器，具备 33MHz 至 112MHz 输入时钟支持 |

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