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DS90CR482VSX/NOPB PDF预览

DS90CR482VSX/NOPB

更新时间： 2024-11-19 13:02:47
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
21页 900K
描述
IC OCTAL LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver

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中文翻译

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DS90CR482VSX/NOPB 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TFQFP, TQFP100,.63SQReach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.32输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mm湿度敏感等级：3
功能数量：8端子数量：100
最高工作温度：70 °C最低工作温度：-10 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装等效代码：TQFP100,.63SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：接收器位数：9
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：280 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
Base Number Matches：1

DS90CR482VSX/NOPB 数据手册

 浏览型号DS90CR482VSX/NOPB的Datasheet PDF文件第2页浏览型号DS90CR482VSX/NOPB的Datasheet PDF文件第3页浏览型号DS90CR482VSX/NOPB的Datasheet PDF文件第4页浏览型号DS90CR482VSX/NOPB的Datasheet PDF文件第5页浏览型号DS90CR482VSX/NOPB的Datasheet PDF文件第6页浏览型号DS90CR482VSX/NOPB的Datasheet PDF文件第7页 
January 2006  
DS90CR481 / DS90CR482  
48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz  
enhancement. To increase bandwidth, the maximum clock  
rate is increased to 112 MHz and 8 serialized LVDS outputs  
are provided. Cable drive is enhanced with a user selectable  
pre-emphasis feature that provides additional output current  
during transitions to counteract cable loading effects. Op-  
tional DC balancing on a cycle-to-cycle basis, is also pro-  
vided to reduce ISI (Inter-Symbol Interference). With pre-  
emphasis and DC balancing, a low distortion eye-pattern is  
provided at the receiver end of the cable. A cable deskew  
capability has been added to deskew long cables of pair-to-  
pair skew of up to +/−1 LVDS data bit time (up to 80 MHz  
Clock Rate). These three enhancements allow cables 5+  
meters in length to be driven.  
General Description  
The DS90CR481 transmitter converts 48 bits of CMOS/TTL  
data into eight LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a ninth LVDS link. Every  
cycle of the transmit clock 48 bits of input data are sampled  
and transmitted. The DS90CR482 receiver converts the  
LVDS data streams back into 48 bits of LVCMOS/TTL data.  
At a transmit clock frequency of 112MHz, 48 bits of TTL data  
are transmitted at a rate of 672Mbps per LVDS data channel.  
Using a 112MHz clock, the data throughput is 5.38Gbit/s  
(672Mbytes/s). At a transmit clock frequency of 112MHz, 48  
bits of TTL data are transmitted at a rate of 672Mbps per  
LVDS data channel. Using a 66MHz clock, the data through-  
put is 3.168Gbit/s (396Mbytes/s).  
The chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
The multiplexing of data lines provides a substantial cable  
reduction. Long distance parallel single-ended buses typi-  
cally require a ground wire per active signal (and have very  
limited noise rejection capability). Thus, for a 48-bit wide  
data and one clock, up to 98 conductors are required. With  
this Channel Link chipset as few as 19 conductors (8 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides an 80% reduction in cable width,  
which provides a system cost savings, reduces connector  
physical size and cost, and reduces shielding requirements  
due to the cables’ smaller form factor.  
Features  
n 3.168 Gbits/sec bandwidth with 66 MHz Clock  
n 5.376 Gbits/sec bandwidth with 112 MHz Clock  
n 65 - 112 MHz input clock support  
n LVDS SER/DES reduces cable and connector size  
n Pre-emphasis reduces cable loading effects  
n Optional DC balance encoding reduces ISI distortion  
n Cable Deskew of +/−1 LVDS data bit time (up to 80  
MHz Clock Rate)  
n 5V Tolerant TxIN and control input pins  
n Flow through pinout for easy PCB design  
n +3.3V supply voltage  
The 48 CMOS/TTL inputs can support a variety of signal  
combinations. For example, 6 8-bit words or 5 9-bit (byte +  
parity) and 3 controls.  
n Transmitter rejects cycle-to-cycle jitter  
n Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard  
The DS90CR481/DS90CR482 chipset is improved over prior  
generations of Channel Link devices and offers higher band-  
width support and longer cable drive with three areas of  
Generalized Block Diagrams (DS90CR481 and DS90CR482)  
20009101  
© 2006 National Semiconductor Corporation  
DS200091  
www.national.com  
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与DS90CR482VSX/NOPB相关器件

型号 品牌 获取价格 描述 数据表
DS90CR483 NSC

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 		48-Bit LVDS Channel Link Serializer/Deserializer
DS90CR483 TI

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 		48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR483_04 NSC

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 		48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR483A TI

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 		DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90CR483AVJD TI

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 		DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90CR483AVJD/NOPB TI

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 		48-bit LVDS channel link serializer with input clock support from 33 MHz to 112 MHz 100-TQ
DS90CR483AVJDX/NOPB TI

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 		48 位 LVDS 通道链接串行器，具备 33MHz 至 112MHz 输入时钟支持 |
DS90CR483SLB TI

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 		LINE DRIVER, QCC128, 0.50 MM PITCH, CSP-128
DS90CR483VJD NSC

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 		48-Bit LVDS Channel Link Serializer/Deserializer
DS90CR483VJD TI

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 		48-Bit Channel Link Serializer - 33-112MHz 100-TQFP -10 to 70

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