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DS25BR100TSDX/NOPB PDF预览

DS25BR100TSDX/NOPB

更新时间: 2024-09-16 14:49:11
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路驱动器
页数 文件大小 规格书
19页 873K
描述
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization 8-WSON -40 to 85

DS25BR100TSDX/NOPB 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:HVSON, SOLCC8,.11,20针数:8
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01风险等级:5.32
差分输出:YES驱动器位数:1
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-XDSO-N8
JESD-609代码:e3长度:3 mm
湿度敏感等级:3功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.11,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:0.8 mm子类别:Line Driver or Receivers
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:0.465 ns宽度:3 mm
Base Number Matches:1

DS25BR100TSDX/NOPB 数据手册

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DS25BR100  
www.ti.com  
SNLS217F MARCH 2007REVISED APRIL 2013  
DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and  
Receive Equalization  
Check for Samples: DS25BR100  
1
FEATURES  
DESCRIPTION  
The DS25BR100 and DS25BR101 are single channel  
3.125 Gbps LVDS buffers optimized for high-speed  
signal transmission over lossy FR-4 printed circuit  
board backplanes and balanced metallic cables. Fully  
differential signal paths ensure exceptional signal  
integrity and noise immunity.  
2
DC - 3.125 Gbps Low Jitter, High Noise  
Immunity, Low Power Operation  
Receive Equalization Reduces ISI Jitter Due to  
Media Loss  
Transmit Pre-Emphasis Drives Lossy  
Backplanes and Cables  
The DS25BR100 and DS25BR101 feature transmit  
pre-emphasis (PE) and receive equalization (EQ),  
making them ideal for use as a repeater device.  
Other LVDS devices with similar IO characteristics  
include the following products. The DS25BR120  
features four levels of pre-emphasis for use as an  
optimized driver device, while the DS25BR110  
features four levels of equalization for use as an  
optimized receiver device. The DS25BR150 is a  
buffer/repeater with the lowest power consumption  
and does not feature transmit pre-emphasis nor  
receive equalization.  
On-Chip 100Input and Output Termination:  
Minimizes Insertion and Return Losses  
Reduces Component Count  
Minimizes Board Space  
DS25BR101 Eliminates On-Chip Input  
Termination for Added Design Flexibility  
7 kV ESD on LVDS I/O Pins Protects Adjoining  
Components  
Small 3 mm x 3 mm WSON-8 Space Saving  
Package  
Wide input common mode range allows the receiver  
to accept signals with LVDS, CML and LVPECL  
levels; the output levels are LVDS. A very small  
package footprint requires minimal space on the  
board while the flow-through pinout allows easy board  
layout. On the DS25BR100 the differential input and  
output is internally terminated with a 100resistor to  
lower return losses, reduce component count and  
further minimize board space. For added design  
flexibility the 100input terminations on the  
DS25BR101 have been eliminated. This elimination  
enables a designer to adjust the termination for  
custom interconnect topologies and layout.  
APPLICATIONS  
Clock and Data Buffering  
Metallic Cable Driving and Equalization  
FR-4 Equalization  
Typical Application  
V
CC  
CML  
LVDS  
ASIC / FPGA  
BR100  
LVPECL  
V
CC  
ASIC / FPGA  
BR100  
LVDS  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  

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