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DS25BR101TSD PDF预览

DS25BR101TSD

更新时间: 2024-09-16 06:54:39
品牌 Logo 应用领域
美国国家半导体 - NSC 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
16页 472K
描述
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

DS25BR101TSD 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:HVSON, SOLCC8,.12,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.46Is Samacsys:N
差分输出:YES驱动器位数:1
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-XDSO-N8
JESD-609代码:e0长度:3 mm
湿度敏感等级:3功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.12,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:0.8 mm子类别:Line Driver or Receivers
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
最大传输延迟:0.465 ns宽度:3 mm
Base Number Matches:1

DS25BR101TSD 数据手册

 浏览型号DS25BR101TSD的Datasheet PDF文件第2页浏览型号DS25BR101TSD的Datasheet PDF文件第3页浏览型号DS25BR101TSD的Datasheet PDF文件第4页浏览型号DS25BR101TSD的Datasheet PDF文件第5页浏览型号DS25BR101TSD的Datasheet PDF文件第6页浏览型号DS25BR101TSD的Datasheet PDF文件第7页 
August 11, 2009  
DS25BR100 / DS25BR101  
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and  
Receive Equalization  
General Description  
Features  
The DS25BR100 and DS25BR101 are single channel 3.125  
Gbps LVDS buffers optimized for high-speed signal trans-  
mission over lossy FR-4 printed circuit board backplanes and  
balanced metallic cables. Fully differential signal paths en-  
sure exceptional signal integrity and noise immunity.  
DC - 3.125 Gbps low jitter, high noise immunity, low power  
operation  
Receive equalization reduces ISI jitter due to media loss  
Transmit pre-emphasis drives lossy backplanes and  
cables  
The DS25BR100 and DS25BR101 feature transmit pre-em-  
phasis (PE) and receive equalization (EQ), making them ideal  
for use as a repeater device. Other LVDS devices with similar  
IO characteristics include the following products. The  
DS25BR120 features four levels of pre-emphasis for use as  
an optimized driver device, while the DS25BR110 features  
four levels of equalization for use as an optimized receiver  
device. The DS25BR150 is a buffer/repeater with the lowest  
power consumption and does not feature transmit pre-em-  
phasis nor receive equalization.  
On-chip 100input and output termination minimizes  
insertion and return losses, reduces component count and  
minimizes board space. The DS25BR101 eliminates the  
on-chip input termination for added design flexibility.  
7 kV ESD on LVDS I/O pins protects adjoining  
components  
Small 3 mm x 3 mm LLP-8 space saving package  
Applications  
Wide input common mode range allows the receiver to accept  
signals with LVDS, CML and LVPECL levels; the output levels  
are LVDS. A very small package footprint requires minimal  
space on the board while the flow-through pinout allows easy  
board layout. On the DS25BR100 the differential input and  
output is internally terminated with a 100resistor to lower  
return losses, reduce component count and further minimize  
board space. For added design flexibility the 100input ter-  
minations on the DS25BR101 have been eliminated. This  
enables a designer to adjust the termination for custom inter-  
connect topologies and layout.  
Clock and data buffering  
Metallic cable driving and equalization  
FR-4 equalization  
Typical Application  
20179110  
© 2009 National Semiconductor Corporation  
201791  
www.national.com  

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