5秒后页面跳转
DS25BR120 PDF预览

DS25BR120

更新时间: 2024-11-09 12:27:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 845K
描述
DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

DS25BR120 数据手册

 浏览型号DS25BR120的Datasheet PDF文件第2页浏览型号DS25BR120的Datasheet PDF文件第3页浏览型号DS25BR120的Datasheet PDF文件第4页浏览型号DS25BR120的Datasheet PDF文件第5页浏览型号DS25BR120的Datasheet PDF文件第6页浏览型号DS25BR120的Datasheet PDF文件第7页 
DS25BR120  
www.ti.com  
SNLS256E MARCH 2007REVISED APRIL 2013  
DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis  
Check for Samples: DS25BR120  
1
FEATURES  
DESCRIPTION  
The DS25BR120 is a single channel 3.125 Gbps  
LVDS buffer optimized for high-speed signal  
transmission over lossy FR-4 printed circuit board  
backplanes and balanced metallic cables. Fully  
differential signal paths ensure exceptional signal  
integrity and noise immunity.  
2
DC - 3.125 Gbps Low Jitter, High Noise  
Immunity, Low Power Operation  
Four Levels of Transmit Pre-Emphasis Drive  
Lossy Backplanes and Cables  
On-Chip 100Input and Output Termination  
Minimizes Insertion and Return Losses,  
Reduces Component Count, and Minimizes  
Board Space  
The DS25BR120 features four levels of pre-emphasis  
(PE) for use as an optimized driver device. Other  
LVDS devices with similar IO characteristics include  
the following products. The DS25BR110 features four  
levels of equalization for use as an optimized receiver  
device, while the DS25BR100 features both pre-  
emphasis and equalization for use as an optimized  
repeater device. The DS25BR150 is a buffer/repeater  
with the lowest power consumption and does not  
7 kV ESD on LVDS I/O pins Protects Adjoining  
Components  
Small 3 mm x 3 mm 8-WSON Space Saving  
Package  
APPLICATIONS  
feature  
transmit  
pre-emphasis  
nor  
receive  
equalization.  
Clock and Data Buffering  
Metallic Cable Driving  
FR-4 Driving  
Wide input common mode range allows the receiver  
to accept signals with LVDS, CML and LVPECL  
levels; the output levels are LVDS. A very small  
package footprint requires minimal space on the  
board while the flow-through pinout allows easy board  
layout. The differential inputs and outputs are  
internally terminated with a 100resistor to lower  
device input and output return losses, reduce  
component count and further minimize board space.  
Typical Application  
PE  
2
CML  
LVDS  
BR120  
ASIC / FPGA  
LVPECL  
ASIC / FPGA  
LVDS  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  

DS25BR120 替代型号

型号 品牌 替代类型 描述 数据表
DS25BR100 TI

功能相似

具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器
DS25BR110 TI

功能相似

具有接收均衡功能的 3.125Gbps LVDS 缓冲器
DS25BR150 TI

功能相似

3.125Gbps LVDS 缓冲器

与DS25BR120相关器件

型号 品牌 获取价格 描述 数据表
DS25BR120_0711 NSC

获取价格

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis
DS25BR120TSD NSC

获取价格

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR120TSD/NOPB TI

获取价格

DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis
DS25BR120TSDX TI

获取价格

IC,REPEATER INTERFACE,LLCC,8PIN,PLASTIC
DS25BR120TSDX/NOPB TI

获取价格

DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis
DS25BR150 NSC

获取价格

3.125 Gbps LVDS Buffer
DS25BR150 TI

获取价格

3.125Gbps LVDS 缓冲器
DS25BR150_0711 NSC

获取价格

3.125 Gbps LVDS Buffer
DS25BR150TSD NSC

获取价格

3.125 Gbps LVDS Buffer
DS25BR150TSD/NOPB TI

获取价格

3.125Gbps LVDS 缓冲器 | NGQ | 8 | -40 to 85