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DS25BR100

更新时间： 2024-11-07 11:13:35
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德州仪器 - TI /
页数 文件大小 规格书
21页 559K
描述
具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器

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DS25BR100 数据手册

 浏览型号DS25BR100的Datasheet PDF文件第2页浏览型号DS25BR100的Datasheet PDF文件第3页浏览型号DS25BR100的Datasheet PDF文件第4页浏览型号DS25BR100的Datasheet PDF文件第5页浏览型号DS25BR100的Datasheet PDF文件第6页浏览型号DS25BR100的Datasheet PDF文件第7页 
DS25BR100  
www.ti.com  
SNLS217F –MARCH 2007–REVISED APRIL 2013  
DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and  
Receive Equalization  
Check for Samples: DS25BR100  
1
FEATURES  
DESCRIPTION  
The DS25BR100 and DS25BR101 are single channel  
3.125 Gbps LVDS buffers optimized for high-speed  
signal transmission over lossy FR-4 printed circuit  
board backplanes and balanced metallic cables. Fully  
differential signal paths ensure exceptional signal  
integrity and noise immunity.  
2
•
DC - 3.125 Gbps Low Jitter, High Noise  
Immunity, Low Power Operation  
•
•
•
Receive Equalization Reduces ISI Jitter Due to  
Media Loss  
Transmit Pre-Emphasis Drives Lossy  
Backplanes and Cables  
The DS25BR100 and DS25BR101 feature transmit  
pre-emphasis (PE) and receive equalization (EQ),  
making them ideal for use as a repeater device.  
Other LVDS devices with similar IO characteristics  
include the following products. The DS25BR120  
features four levels of pre-emphasis for use as an  
optimized driver device, while the DS25BR110  
features four levels of equalization for use as an  
optimized receiver device. The DS25BR150 is a  
buffer/repeater with the lowest power consumption  
and does not feature transmit pre-emphasis nor  
receive equalization.  
On-Chip 100Ω Input and Output Termination:  
–
–
–
Minimizes Insertion and Return Losses  
Reduces Component Count  
Minimizes Board Space  
•
•
•
DS25BR101 Eliminates On-Chip Input  
Termination for Added Design Flexibility  
7 kV ESD on LVDS I/O Pins Protects Adjoining  
Components  
Small 3 mm x 3 mm WSON-8 Space Saving  
Package  
Wide input common mode range allows the receiver  
to accept signals with LVDS, CML and LVPECL  
levels; the output levels are LVDS. A very small  
package footprint requires minimal space on the  
board while the flow-through pinout allows easy board  
layout. On the DS25BR100 the differential input and  
output is internally terminated with a 100Ω resistor to  
lower return losses, reduce component count and  
further minimize board space. For added design  
flexibility the 100Ω input terminations on the  
DS25BR101 have been eliminated. This elimination  
enables a designer to adjust the termination for  
custom interconnect topologies and layout.  
APPLICATIONS  
•
•
•
Clock and Data Buffering  
Metallic Cable Driving and Equalization  
FR-4 Equalization  
Typical Application  
V
CC  
CML  
LVDS  
ASIC / FPGA  
BR100  
LVPECL  
V
CC  
ASIC / FPGA  
BR100  
LVDS  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  
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DS25BR100 替代型号

型号 品牌 替代类型 描述 数据表
DS25BR110 TI

功能相似

 具有接收均衡功能的 3.125Gbps LVDS 缓冲器
DS25BR150 TI

功能相似

 3.125Gbps LVDS 缓冲器
DS25BR120 TI

功能相似

 DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

与DS25BR100相关器件

型号 品牌 获取价格 描述 数据表
DS25BR100_0711 NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR100_09 NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR100TSD NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR100TSD/NOPB NSC

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 		IC LINE DRIVER, DSO8, 3 X 3 MM, LLP-8, Line Driver or Receiver
DS25BR100TSD/NOPB TI

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 		具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 | NGQ | 8
DS25BR100TSDX NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR100TSDX/NOPB TI

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization 8-WSON -40 to 8
DS25BR101 NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR101 TI

获取价格

 		具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器
DS25BR101TSD NSC

获取价格

 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

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