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DS25BR100TSD PDF预览

DS25BR100TSD

更新时间： 2024-11-09 04:15:11
品牌 Logo 应用领域
美国国家半导体 - NSC 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
14页 448K
描述
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

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中文翻译

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DS25BR100TSD 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：3 X 3 MM, LLP-8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.33Is Samacsys：N
差分输出：YES驱动器位数：1
输入特性：DIFFERENTIAL接口集成电路类型：LINE DRIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-XDSO-N8
JESD-609代码：e0长度：3 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVSON封装等效代码：SOLCC8,.11,20
封装形状：SQUARE封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：0.8 mm子类别：Line Driver or Receivers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
最大传输延迟：0.465 ns宽度：3 mm
Base Number Matches：1

DS25BR100TSD 数据手册

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November 6, 2007  
DS25BR100  
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and  
Receive Equalization  
General Description  
Features  
The DS25BR100 is a single channel 3.125 Gbps LVDS buffer  
optimized for high-speed signal transmission over lossy FR-4  
printed circuit board backplanes and balanced metallic ca-  
bles. Fully differential signal paths ensure exceptional signal  
integrity and noise immunity.  
DC - 3.125 Gbps low jitter, high noise immunity, low power  
operation  
Receive equalization reduces ISI jitter due to media loss  
■
■
■
Transmit pre-emphasis drives lossy backplanes and  
cables  
The DS25BR100 features transmit pre-emphasis (PE) and  
receive equalization (EQ), making it ideal for use as a re-  
peater device. Other LVDS devices with similar IO character-  
istics include the following products. The DS25BR120  
features four levels of pre-emphasis for use as an optimized  
driver device, while the DS25BR110 features four levels of  
equalization for use as an optimized receiver device. The  
DS25BR150 is a buffer/repeater with the lowest power con-  
sumption and does not feature transmit pre-emphasis nor  
receive equalization.  
On-chip 100Ω input and output termination minimizes  
insertion and return losses, reduces component count and  
minimizes board space  
7 kV ESD on LVDS I/O pins protects adjoining  
components  
■
■
■
Small 3 mm x 3 mm LLP-8 space saving package  
Applications  
Clock and data buffering  
■
■
■
Wide input common mode range allows the receiver to accept  
signals with LVDS, CML and LVPECL levels; the output levels  
are LVDS. A very small package footprint requires minimal  
space on the board while the flow-through pinout allows easy  
board layout. The differential inputs and outputs are internally  
terminated with a 100Ω resistor to lower device input and out-  
put return losses, reduce component count, and further min-  
imize board space.  
Metallic cable driving and equalization  
FR-4 equalization  
Typical Application  
20179110  
© 2007 National Semiconductor Corporation  
201791  
www.national.com  
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与DS25BR100TSD相关器件

型号 品牌 获取价格 描述 数据表
DS25BR100TSD/NOPB NSC

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 		IC LINE DRIVER, DSO8, 3 X 3 MM, LLP-8, Line Driver or Receiver
DS25BR100TSD/NOPB TI

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 		具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 | NGQ | 8
DS25BR100TSDX NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR100TSDX/NOPB TI

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization 8-WSON -40 to 8
DS25BR101 NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR101 TI

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 		具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器
DS25BR101TSD NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR101TSD/NOPB TI

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 		具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 | NGQ | 8
DS25BR101TSDE/NOPB TI

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 		具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 | NGQ | 8
DS25BR101TSDX NSC

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 		3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

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